Electronically tuned RF termination
AssigneeSkyworks Solutions, Inc.
InventorDavid Steven Ripley
Life of this patent
Estimating the term…
Abstract
Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).
Claims20
A tunable impedance circuit comprising:
- a transistor assembly having two terminals and a first control input, the transistor assembly including a plurality of transistors electrically connected in series between the two terminals, the plurality of transistors arranged to provide a first impedance between the two terminals based upon a control signal received at the first control input, each transistor of the plurality of transistors including a gate coupled to the first control input;
- a plurality of replica transistors electrically connected together in series and having a second control input, the plurality of replica transistors arranged to provide a replica impedance based upon the control signal received at the second control input, each replica transistor of the plurality of replica transistors including a gate coupled to the second control input;
- and
- a control circuit configured to generate the control signal based upon at least one of a reference voltage across the plurality of replica transistors and a current through the plurality of replica transistors, the control circuit being further configured to maintain the replica impedance by adjusting the control signal.
A tunable impedance circuit comprising:
- a plurality of transistors electrically connected together in series to provide two terminals and a first control input, the plurality of transistors arranged to provide an impedance between the two terminals based upon a control signal received at the first control input, each transistor of the plurality of transistors including a gate coupled to the first control input;
- a current source to provide a current into one of the two terminals and through the plurality of transistors;
- a sensing circuit configured to sense a voltage between the two terminals and to generate the control signal based upon the voltage, the sensing circuit being further configured to maintain the impedance by adjusting the control signal;
- and
- a plurality of termination transistors connected together in series and arranged to receive the control signal at a second control input to provide a termination impedance based upon the control signal, each transistor of the plurality of termination transistors including a gate coupled to the second control input.
A method of controlling impedance of a plurality of transistors operating in a triode region of operation, the method comprising:
- providing a control signal to a first control input of a plurality of replica transistors electrically connected in series causing the plurality of replica transistors to operate in a triode region, each replica transistor of the plurality of replica transistors including a gate coupled to the first control input;
- providing a current through the plurality of replica transistors, the current entering the plurality of replica transistors at a first terminal and exiting the plurality of replica transistors at a second terminal;
- sensing a voltage between the first terminal and the second terminal, the voltage being across the plurality of replica transistors;
- adjusting the control signal to maintain a desired ratio of the voltage to the current;
- and
- providing the control signal to a second control input of the plurality of transistors, the plurality of transistors being electrically connected in series and each transistor of the plurality of transistors including a gate coupled to the second control input.
Dependencies are inferred from the claim text.