US 11,705,485 B2 · LDMOS transistors with breakdown voltage clamps

Abstract

A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.

Claims7

Dependent claims

A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp, comprising:

a drain n+ region;
a source n+ region;
a gate;
an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction;
a p-type reduced surface field (PRSF) layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction;
a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction, the drain n+ region being disposed over the PBL in the thickness direction;
and
an n-type drift (NDRFT) region disposed over the PRSF layer and adjacent to the NRSF layer in the lateral direction, wherein the drain n+ region is disposed in the NDRFT region.

5 more elements

Dependencies are inferred from the claim text.

LDMOS transistors with breakdown voltage clamps

Life of this patent

LDMOS transistors with breakdown voltage clamps

Life of this patent

Abstract

Claims7