Networked computer with multiple embedded rings

A network comprising a first processor interconnected with a second processor, each processor comprising one or more of:

• a plurality of processing units arranged on a chip, each processing unit being configured to execute program code;
• an on-chip interconnect arranged to enable the program code to run on the processing units to exchange data between the processing units, wherein the on-chip interconnect comprises multiple groups of exchange paths, each group connected to receive data from a corresponding group of the processing units;
• a plurality of external interfaces configured to communicate data off chip as packets, each packet having a destination address identifying a destination of the packet, a first external interface of the first processor being connected by an external link to a corresponding first external interface of the second processor;
• a plurality of exchange blocks connected to the groups of exchange paths;
• and
• a routing bus configured to route packets between the exchange blocks and the external interfaces;
• wherein processing units of the first processor are configured to generate off chip packets addressed to processing units of the second processor such that a group of processing units serviced by a first exchange block on the first processor are configured to address off chip packets to a group of processing units on the second processor serviced by a corresponding first exchange block of the second processor, and
• further wherein the routing bus is configured to route packets from certain exchange blocks only to certain external interfaces and wherein the routing bus is configured to trap as an error packets which are incorrectly addressed by comparing an address of a packet with routing requirements in a routing register.

A network comprising a first processor interconnected with a second processor, each processor comprising one or more of:

• a plurality of processing units arranged on a chip, each processing unit being configured to execute program code;
• an on-chip interconnect arranged to enable the program code to run on the processing units to exchange data between the processing units, wherein the on-chip interconnect comprises multiple groups of exchange paths, each group connected to receive data from a corresponding group of the processing units;
• a plurality of external interfaces configured to communicate data off chip as packets, each packet having a destination address identifying a destination of the packet, a first external interface of the first processor being connected by an external link to a corresponding first external interface of the second processor;
• a plurality of exchange blocks connected to the groups of exchange paths;
• and
• a routing bus configured to route packets between the exchange blocks and the external interfaces;
• wherein processing units of the first processor are configured to generate off chip packets addressed to processing units of the second processor such that a group of processing units serviced by a first exchange block on the first processor are configured to address off chip packets to a group of processing units on the second processor serviced by a corresponding first exchange block of the second processor, and
• further wherein the routing bus has multiple lanes, each lane being unidirectional.

A network comprising a first processor interconnected with a second processor, each processor comprising one or more of:

• a plurality of processing units arranged on a chip, each processing unit being configured to execute program code;
• an on-chip interconnect arranged to enable the program code to run on the processing units to exchange data between the processing units, wherein the on-chip interconnect comprises multiple groups of exchange paths, each group connected to receive data from a corresponding group of the processing units;
• a plurality of external interfaces configured to communicate data off chip as packets, each packet having a destination address identifying a destination of the packet, a first external interface of the first processor being connected by an external link to a corresponding first external interface of the second processor;
• a plurality of exchange blocks connected to the groups of exchange paths;
• and
• a routing bus configured to route packets between the exchange blocks and the external interfaces;
• wherein processing units of the first processor are configured to generate off chip packets addressed to processing units of the second processor such that a group of processing units serviced by a first exchange block on the first processor are configured to address off chip packets to a group of processing units on the second processor serviced by a corresponding first exchange block of the second processor,
• wherein the first processor has a second interface for connecting to a third processor, and wherein the first and second interfaces lie in the second portion of the chip, and
• wherein the first processor has a third external interface which is connected to a fourth processor in a southern orientation with respect to the first processor, and
• further wherein logical identifiers are allocated to each of the second, third and fourth processors which are connected to the first processor, and wherein the first processor is configured to only address packets to these logical identifiers.

A network comprising a first processor interconnected with a second processor, each processor comprising one or more of:

• a plurality of processing units arranged on a chip, each processing unit being configured to execute program code;
• an on-chip interconnect arranged to enable the program code to run on the processing units to exchange data between the processing units, wherein the on-chip interconnect comprises multiple groups of exchange paths, each group connected to receive data from a corresponding group of the processing units;
• a plurality of external interfaces configured to communicate data off chip as packets, each packet having a destination address identifying a destination of the packet, a first external interface of the first processor being connected by an external link to a corresponding first external interface of the second processor;
• a plurality of exchange blocks connected to the groups of exchange paths;
• and
• a routing bus configured to route packets between the exchange blocks and the external interfaces;
• wherein processing units of the first processor are configured to generate off chip packets addressed to processing units of the second processor such that a group of processing units serviced by a first exchange block on the first processor are configured to address off chip packets to a group of processing units on the second processor serviced by a corresponding first exchange block of the second processor, and
• further wherein the first processor has additional external interfaces connected to corresponding additional processors, and wherein each processor has three processors connected directly to it and is configured to operate a routing domain having respective first to fourth logical identifiers to identify itself and each of those three connected processors.

A network comprising a first processor interconnected with a second processor, each processor comprising one or more of:

• a plurality of processing units arranged on a chip, each processing unit being configured to execute program code;
• an on-chip interconnect arranged to enable the program code to run on the processing units to exchange data between the processing units, wherein the on-chip interconnect comprises multiple groups of exchange paths, each group connected to receive data from a corresponding group of the processing units;
• a plurality of external interfaces configured to communicate data off chip as packets, each packet having a destination address identifying a destination of the packet, a first external interface of the first processor being connected by an external link to a corresponding first external interface of the second processor;
• a plurality of exchange blocks connected to the groups of exchange paths;
• and
• a routing bus configured to route packets between the exchange blocks and the external interfaces;
• wherein processing units of the first processor are configured to generate off chip packets addressed to processing units of the second processor such that a group of processing units serviced by a first exchange block on the first processor are configured to address off chip packets to a group of processing units on the second processor serviced by a corresponding first exchange block of the second processor, and
• further wherein the routing bus has multiple lanes, each lane being unidirectional, and wherein each chip has four portions corresponding to respective edges of the chip, and wherein a first set of the lanes are southgoing between a top edge and a bottom edge, and a second set of the lanes are northgoing between the bottom edge and the top edge.

A processor comprising:

• an on-chip interconnect configured to exchange data among a plurality of processing units, wherein the on-chip interconnect comprises multiple groups of exchange paths, each group of exchange paths connected to receive data from a corresponding group of the processing units;
• a plurality of external interfaces configured to communicate data off chip as off chip packets having destination addresses, wherein the processor is interconnected with an additional processor, and wherein a first external interface of the processor is connected by an external link to a corresponding first external interface of the additional processor;
• a plurality of exchange blocks connected to the groups of exchange paths;
• and
• a routing bus configured to route packets between the exchange blocks and the external interfaces;
• wherein the plurality of processing units of the processor are configured to generate the off chip packets addressed to another plurality of processing units of the additional processor such that a group of processing units serviced by a first exchange block on the processor are configured to address the off chip packets to a group of processing units on the additional processor serviced by a corresponding first exchange block of the additional processor, and
• wherein the processor comprises a first group of the exchange blocks in a first portion of a chip and a second group of the exchange blocks in a second portion of the chip, wherein the on-chip interconnect extends between the exchange blocks of the first group in the first portion of the chip and the exchange blocks of the second group in the second portion of the chip.