US 11,700,732 B2Granted

Memory device including different dielectric structures between blocks

AssigneeMicron Technology, Inc.

InventorsPaolo Tessariol, David H. Wells, Umberto Maria Meotto

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Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

Claims18

Dependent claims

An apparatus comprising:

levels of conductive materials interleaved with levels of dielectric materials;
memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials;
a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials;
a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials;
and
the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into a first portion, a second portion, and a third portion, the first portion including first control gates associated with first memory cell strings of the memory cell strings, the first second including second control gates associated with second memory cell strings of the memory cell strings, the third portion including third control gates associated with third memory cell strings of the memory cell strings, wherein the first memory cell strings are included in a first block of memory cells, the second memory cell strings are included in a second block of memory cells, the third memory cell strings are included in a third block of memory cells, the first dielectric structure is between the first and second blocks, the second dielectric structure is between the second and third blocks, and wherein,
the first dielectric structure is between the first and second portions and includes a first width, and
the second dielectric structure is between the second and third portions and includes a second width, and the first width is less than the second width.

5 more elements

An apparatus comprising:

a first block including first memory cells and a first group of control gates for the first memory cells, and first dielectric materials interleaved with the first group of control gates;
a second block including second memory cells and a second group of control gates for the second memory cells, and second dielectric materials interleaved with the second group of control gates;
a third block including third memory cells and a third group of control gates for the third memory cells, and third dielectric materials interleaved with the third group of control gates;
a first dielectric structure between the first and second blocks and electrically separating the first group of control gates from the second group of control gates;
and
a second dielectric structure between the second and third blocks and electrically separating the second group of control gates from the third group of control gates, wherein,
the first dielectric materials of the first block include a first dielectric material including a first edge adjacent the first dielectric structure,
the second dielectric materials of the second block include a second dielectric material including a second edge adjacent the first dielectric structure, and a third edge adjacent the second dielectric structure,
the third dielectric materials of the third block include a third dielectric material including a fourth edge adjacent the second dielectric structure, wherein the first, second, and third dielectric materials are located on a same level of the apparatus, and
a distance between the first and second edges is less than a distance between the third and fourth edges.

7 more elements

An apparatus comprising:

a first block including first memory cells and a first group of control gates for the first memory cells;
a second block including second memory cells and a second group control gates for the second memory cells;
a third block including third memory cells and a third group of control gates for the third memory cells;
a first dielectric structure between the first and second blocks and electrically separating the first group of control gates of the first block from the second group of control gates of the second block;
and
a second dielectric structure between the second and third blocks and electrically separating the second group of control gates of the second block from the third group of control gates of the third block, wherein,
the first group of control gates of the first block includes a first control gate including a first edge adjacent the first dielectric structure,
the second group of control gates of the second block includes a second control gate including a second edge adjacent the first dielectric structure, and a third edge adjacent the second dielectric structure,
the third group of control gates of the third block includes a third control gate including a fourth edge adjacent the second dielectric structure, wherein the first, second, and third control gates are located on a same level of the apparatus, and
a distance between the first and second edges is less than a distance between the third and fourth edges.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/146,193Filed 11 Jan 2021
Published: US 2022/0223613 A114 Jul 2022
Granted: 11 Jul 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout
H10B 43/50
EEPROM devices comprising charge-trapping gate insulators: characterised by the boundary region between the core and peripheral circuit regions
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/50
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the boundary region between the core…