Stacked structure for a vertical memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsIl-Woo Kim, Sang-Ho Rha, Byoung-Deog Choi, Ik-Soo Kim, Min-Jae Oh
Life of this patent
Estimating the term…
Loading patent…
AssigneeSamsung Electronics Co., Ltd.
InventorsIl-Woo Kim, Sang-Ho Rha, Byoung-Deog Choi, Ik-Soo Kim, Min-Jae Oh
Estimating the term…
A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.
A stacked structure for a vertical memory device, the stacked structure comprising:
A stacked structure for a vertical memory device, the stacked structure comprising:
Dependencies are inferred from the claim text.