Non-volatile memory device

A nonvolatile semiconductor memory device comprising:

• a plurality of memory cells stacked in a first direction and electrically connected in series;
• a source layer provided below the memory cells;
• and
• a bit line provided above the memory cells,
• at least one of the memory cells including:
• a control gate electrode;
• a first channel extending in the first direction through the control gate electrode, one end of the first channel being electrically connected to the bit line and another end of the first channel being electrically connected to the source layer;
• a first insulating core film provided inside the first channel;
• a charge storage portion including a conductor provided between the control gate electrode and the first channel;
• a first insulating portion surrounding the conductor between the control gate electrode and the first channel;
• and
• a second insulating portion including a stacked structure provided between the control gate electrode and the first insulating portion, the stacked structure including a first film and a second film each having a dielectric constant different from each other,
• a width of the conductor in the first direction being narrower than a width of the control gate electrode in the first direction, and
• the control gate electrode surrounding an outer periphery of the charge storage portion via the second insulating portion in a plane perpendicular to the first direction.