Semiconductor memory structure and method for manufacturing the same
AssigneeWinbond Electronics Corp.
InventorHung-Yu Wei
Life of this patent
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Abstract
A semiconductor structure includes a semiconductor substrate including a first active region and a chop region. The semiconductor structure also includes a source/drain region disposed in the first active region, an isolation structure disposed in the chop region, and a gate structure extending at least across the isolation structure in the chop region. The gate structure includes a gate electrode layer and a gate lining layer lining on the gate electrode layer. The gate lining layer includes a first portion having an upper surface that is lower than a bottom surface of the source/drain region.
Claims20
A semiconductor memory structure, comprising:
- a semiconductor substrate comprising a first active region and a chop region;
- a source/drain region disposed in the first active region;
- an isolation structure disposed in the chop region;
- a first gate structure extending at least across the isolation structure in the chop region, wherein the first gate structure comprises a first gate electrode layer and a first gate lining layer lining on the first gate electrode layer, and an upper surface of the first gate lining layer is lower than a bottom surface of the source/drain region;
- a capping layer disposed on the first gate structure;
- and
- an air gap between the capping layer and the first gate lining layer.
A semiconductor memory structure, comprising:
- a semiconductor substrate;
- a first gate structure embedded in the semiconductor substrate, wherein the first gate structure comprises a first gate lining layer;
- a second gate structure embedded in the semiconductor substrate, wherein the second gate structure comprises a second gate lining layer;
- and
- a source/drain region disposed in the semiconductor substrate, wherein a bottom surface of the source/drain region is higher than an upper surface of the first gate lining layer and is lower than an upper surface of the second gate lining layer.
A method for forming a semiconductor memory structure, comprising:
- providing a semiconductor substrate, the semiconductor substrate comprising a chop region and an active region;
- forming a first gate structure extending across the chop region and forming a second gate structure extending across the active region, wherein each of the first gate structure and the second gate structure comprises a gate electrode layer and a gate lining layer lining on the gate electrode layer;
- forming a patterned mask layer covering the second gate structure and exposing the first gate structure;
- using the patterned mask layer, etching the gate lining layer of the first gate structure;
- and
- forming a source/drain region in the active region, wherein after etching the gate lining layer of the first gate structure, an upper surface of the gate lining layer of the first gate structure is lower than a bottom surface of the source/drain region.
Dependencies are inferred from the claim text.