US 11,700,723 B2 · Semiconductor memory device

Abstract

A semiconductor memory device, including a first semiconductor pattern, and a second semiconductor pattern separated from the first semiconductor pattern in a vertical direction; a first bit line electrically connected to a first source/drain region of the first semiconductor pattern, and a second bit line electrically connected to a first source/drain region of the second semiconductor pattern; a word line structure in contact with the first semiconductor pattern and the second semiconductor pattern; and a first data storage element electrically connected to a second source/drain region of the first semiconductor pattern, and a second data storage element electrically connected to a second source/drain region of the second semiconductor pattern, wherein the first semiconductor pattern and the second semiconductor pattern are monocrystalline, and wherein a crystal orientation of the first semiconductor pattern is different from a crystal orientation of the second semiconductor pattern.

Claims20

Dependent claims

A semiconductor memory device comprising:

a first semiconductor pattern, and a second semiconductor pattern separated from the first semiconductor pattern in a vertical direction;
a first bit line electrically connected to a first source/drain region of the first semiconductor pattern, and a second bit line electrically connected to a first source/drain region of the second semiconductor pattern;
a word line structure in contact with the first semiconductor pattern and the second semiconductor pattern;
and
a first data storage element electrically connected to a second source/drain region of the first semiconductor pattern, and a second data storage element electrically connected to a second source/drain region of the second semiconductor pattern,
wherein the first semiconductor pattern and the second semiconductor pattern are monocrystalline, and
wherein a crystal orientation of the first semiconductor pattern is different from a crystal orientation of the second semiconductor pattern,
wherein at least one of the first semiconductor pattern and the second semiconductor pattern includes a lattice defect extending to a bottom surface or top surface of the at least one of the first semiconductor pattern and the second semiconductor pattern.

5 more elements

A semiconductor memory device comprising:

a plurality of semiconductor patterns arranged in a vertical direction and a first horizontal direction, wherein each of the plurality of semiconductor patterns extends in a second horizontal direction;
a plurality of insulating layers separating the plurality of semiconductor patterns in the vertical direction;
a bit line electrically connected to respective first source/drain regions of some of the plurality of semiconductor patterns;
a word line structure in contact with the some of the plurality of semiconductor patterns;
and
a plurality of data storage elements electrically connected to respective second source/drain regions of the plurality of semiconductor patterns,
wherein the plurality of semiconductor patterns are monocrystalline, and
wherein a crystal orientation of at least one of the plurality of semiconductor patterns is different from a crystal orientation of another one of the plurality of semiconductor patterns, and
wherein the at least one of plurality of semiconductor patterns includes a lattice defect extending to a bottom surface or top surface of the at least one of the plurality of semiconductor patterns.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20