Memory device with air gaps for reducing capacitive coupling

A memory device, comprising:

• an active region disposed in a substrate;
• a word line disposed in the substrate, wherein the word line is intersected with the active region;
• plurality of contact structures disposed on the substrate, wherein the contact structures are located at a side of the word line, and electrically connected to the active region;
• a first conductive layer and a second conductive layer disposed over the substrate, wherein the contact structure are covered by the first and second conductive layers;
• a plurality of conductive pillars overlapped with and electrically connected to the contact structures, wherein the first conductive layer is shaped to form the conductive pillars;
• a plurality of landing pads covering and electrically connecting to the conductive pillars respectively, wherein a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad, wherein the second conductive layer is shaped to form the landing pads;
• and
• a plurality of dielectric layers, one of the dielectric layers configured as a thicker dielectric layer laterally surrounding the conductive pillars and the landing pads, wherein the dielectric layers are stacked between the substrate and the first conductive layer;
• and
• a plurality of air gaps being sealed at the thicker dielectric layer and alternating with the conductive pillars.