Packet switch and method of setting time slot
AssigneeFujitsu Limited
InventorsNorikazu Hikimochi, Kazuto Nishimura, Yoshikazu Sabetto
Life of this patent
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Abstract
A packet switch includes a memory, and a processor coupled to the memory and configured to learn a pattern of a high-priority packet having a cyclicity, monitor a burst end point of the high-priority packet, based on a result of the learning, detect a shift of a time slot of the burst end point when a traffic flow rate of the high-priority packet changes, and determine the time slot to close transmission of a non-priority packet, based on the shift of the time slot.
Claims8
A packet switch comprising:
- a memory;
- and
- a processor coupled to the memory and configured to:
- learn a pattern of a high-priority packet having a cyclicity;
- monitor a burst end point of the high-priority packet, based on a result of the learning;
- detect a shift of a time slot of the burst end point when a traffic flow rate of the high-priority packet changes;
- and
- determine the time slot to close transmission of a non-priority packet, based on the shift of the time slot.
A method of setting a time slot, the method causing a computer to execute a process, the process comprising:
- learning a pattern of a high-priority packet having a cyclicity;
- monitoring a burst end point of the high-priority packet, based on a result of the learning;
- detecting a shift of the time slot of the burst end point when a traffic flow rate of the high-priority packet changes;
- and
- determining the time slot to close transmission of a non-priority packet, based on the shift of the time slot.
Dependencies are inferred from the claim text.