Receiving circuit of deserializer

A receiving circuit of a deserializer, the receiving circuit receiving an input signal, comprising:

• a signal receiving terminal configured to receive the input signal;
• a link equalizer circuit having a first input terminal electrically coupled to the signal receiving terminal;
• an out-of-band signaling (OOBS) circuit having a second input terminal electrically coupled to the signal receiving terminal;
• a first capacitor having a first terminal and a second terminal, wherein the first terminal is electrically coupled to the signal receiving terminal, and the second terminal is electrically coupled to one of the link equalizer circuit and the OOBS circuit;
• a second capacitor having a third terminal and a fourth terminal, wherein the third terminal is electrically coupled to the signal receiving terminal, and the fourth terminal is electrically coupled to the one of link equalizer circuit and the OOBS circuit;
• a first resistor having a fifth terminal and a sixth terminal, wherein the fifth terminal is electrically coupled to a first reference voltage, and the sixth terminal is electrically coupled to the signal receiving terminal;
• a second resistor having a seventh terminal and an eighth terminal, wherein the seventh terminal is electrically coupled to a second reference voltage, and the eighth terminal is electrically coupled to one of the link equalizer circuit and the OOBS circuit;
• and
• a buffer circuit having a third input terminal and an output terminal, wherein the third input terminal is configured to receive a voltage, and the output terminal is electrically coupled to one of the link equalizer circuit and the OOBS circuit;
• wherein the first input terminal of the link equalizer circuit and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable.