Passive sample-and-hold analog-to-digital converter with split reference voltage

A successive-approximation analog-to-digital converter (ADC) circuit, comprising:

• a voltage comparator;
• one or more sample capacitors, each having a first end connected to an input of the comparator;
• one or more most-significant-bit (MSB) digital-to-analog converter (DAC) capacitors, each having a first end connected to an input of the comparator;
• one or more least-significant-bit (LSB) DAC capacitors, each having a first end connected to the input of the comparator;
• one or more first switch devices corresponding to each sample capacitor and configured to selectively connect the second end of the respective sample capacitor to (a) an input voltage, for the duration of a sampling phase, and (b) a ground reference, during portions of a conversion phase;
• one or more second switch devices corresponding to each MSB capacitor and configured to selectively connect the second end of the respective MSB capacitor to (c) the ground reference, during portions of a conversion phase, and (d) a first conversion reference voltage for other portions of the conversion phase;
• and
• one or more third switch devices corresponding to each LSB capacitor and configured to selectively connect the second end of the respective LSB capacitor between (e) the ground reference, during portions of the conversion phase, and (f) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first conversion reference voltage.