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US 11,700,002 B2Granted
Network-on-chip (NOC) with flexible data width
AssigneeIntel Corporation
InventorsSharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Abstract
Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
Claims20
An integrated circuit comprising:
- a first programmable logic circuit;
- a second programmable logic circuit;
- and
- a network-on-chip (NoC) between the first programmable logic circuit and the second programmable logic circuit, wherein the NoC has a configurable data width, and wherein the NoC comprises:
- a plurality of data paths that collectively have the configurable data width;
- and
- a plurality of packet switches interconnected to each other through respective paths of the plurality of data paths, wherein a first packet switch of the plurality of packet switches:
- receives a first packet from the first programmable logic circuit, wherein the first packet comprises a destination identifier;
- performs a first lookup operation in a table based on the destination identifier;
- and
- transmits, using one of the data paths of the plurality of data paths, the first packet to a second packet switch of the plurality of packet switches based at least in part on a result of the first lookup operation.
8 more elements
The An integrated circuit comprising:
- a first programmable logic circuit;
- a second programmable logic circuit;
- a network-on-chip (NoC) access circuit that receives a first packet from the first programmable logic circuit, wherein the first packet comprises a destination identifier;
- a network-on-chip (NoC) egress circuit;
- and
- a network-on-chip (NoC) coupled to the first programmable logic circuit via the NoC access circuit and coupled to the second programmable logic circuit via the NoC egress circuit, wherein the NoC is configurable to transmit data based on a data width of a plurality of data widths based on a parameter, wherein the NoC is programmable to transmit the data via any of a plurality of routes, and wherein the NoC comprises:
- a plurality of data paths that collectively have the data width of the plurality of data widths;
- and
- a plurality of packet switches interconnected to each other through respective paths of the plurality of data paths, wherein a first packet switch of the plurality of packet switches:
- receives the first packet from the first programmable logic circuit;
- performs a first lookup operation in a table based on the destination identifier;
- and
- transmits, using one of the data paths of the plurality of data paths, the first packet to a second packet switch of the plurality of packet switches based at least in part on a result of the first lookup operation.
10 more elements
A system comprising:
- a programmable logic device comprising:
- a first programmable logic circuit;
- a second programmable logic circuit;
- and
- a network-on-chip (NoC) between the first programmable logic circuit and the second programmable logic circuit, wherein the NoC has a configurable data width, and wherein the NoC comprises:
- a plurality of data paths associated with the configurable data width;
- and
- a plurality of packet switches interconnected to each other through respective paths of the plurality of data paths, wherein a first packet switch of the plurality of packet switches:
- receives a first packet, wherein the first packet comprises a destination identifier associated with the first programmable logic circuit;
- performs a first lookup operation in a table based on the destination identifier;
- and
- transmits, using one of the data paths of the plurality of data paths, the first packet to a second packet switch of the plurality of packet switches based at least in part on a result of the first lookup operation;
- and
- a memory that stores the first packet, wherein the memory is configurable to send the first packet as a transaction from the memory to the first programmable logic circuit;
- and
- an interfacing block that couples the programmable logic device to the memory.
13 more elements
Dependencies are inferred from the claim text.