CAN bus transmitter
AssigneeMicrochip Technology Incorporated
InventorWolfgang Roeper
Life of this patent
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Abstract
A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.
Claims19
A controller area network (CAN) domino driver circuit, comprising:
- a CAN high (CANH) leg having an input coupled to a transmit data (TXD) signal and a first output for coupling to a CANH circuit of a CAN bus;
- and
- a CAN low (CANL) leg having an input coupled to the TXD signal and a second output for coupling to a CANL circuit of the CAN bus;
- wherein a logic level change of the TXD signal will generate logic level changes at the first and second outputs of the CANH and CANL legs;
- wherein the CANH leg comprises:
- a P-channel metal oxide semiconductor field effect transistor (PMOSFET);
- a first resistor;
- a cascode PMOSFET;
- a first diode;
- and
- an inverting buffer;
- wherein
- the PMOSFET source is coupled to a first voltage level, the PMOSFET gate is coupled to an output of the first buffer, and the PMOSFET drain is coupled to a first node of the first resistor;
- the cascode PMOSFET source is coupled to a second node of the first resistor, the cascode PMOSFET gate is coupled to a bias voltage, and the cascade PMOSFET drain is coupled to an anode of the first diode;
- a cathode of the first diode is coupled to the first output of the CANH leg;
- and
- an input of the first buffer amplifier is coupled to the input of the CANH leg.
A controller area network (CAN) bus driver circuit, comprising:
- a plurality of CAN domino driver circuits, respective CAN domino driver circuits having an input and first and second outputs for respective coupling to CANH and CANL terminals of a CAN bus;
- a plurality of time delay circuits, respective time delay circuits having an input and an output;
- the input of a first one of the plurality of CAN domino driver circuits and the input of a first one of the plurality of delay circuits coupled to a node, the node for coupling to a transmit data (TXD) signal;
- and
- the inputs of respective subsequent one of the plurality of delay circuits are coupled to the output of a previous one of the plurality of time delay circuits, and to the inputs of each subsequent one of the plurality of CAN domino driver circuit are coupled to the output of the previous one of the plurality of time delay circuits, such that a respective time delay circuit is between respective ones of the plurality of CAN domino driver circuits after the first one,
- wherein the plurality of time delay circuits have adjustable time delays.
A method for driving a controller area network (CAN) bus, said method comprising:
- providing a plurality of CAN domino driver circuits, respective CAN domino driver circuits having an input and first and second outputs for respective coupling to CANH and CANL terminals of a CAN bus;
- providing a plurality of time delay circuits, respective time delay circuits having an input and an output;
- coupling the input of a first one of the plurality of CAN domino driver circuits and the input of a first one of the plurality of delay circuits to a node, the node for coupling to a transmit data (TXD) signal;
- dynamically adjusting time delays of at least some of the plurality of time delay circuits;
- and
- coupling the inputs of respective subsequent ones of the plurality of delay circuits to the output of a previous one of the plurality of time delay circuits, and to the inputs of respective subsequent ones of the plurality of CAN domino driver circuits to the output of the previous one of the plurality of time delay circuits, such that a respective time delay circuit is between respective ones the plurality of CAN domino driver circuits after the first one.
Dependencies are inferred from the claim text.