Signal sampling with offset calibration

A method, comprising:

• receiving, at a gate of a first transistor, a first input signal;
• receiving, at a gate of a second transistor, a second input signal, wherein a source node of the second transistor is coupled with a source node of the first transistor via a resistor;
• coupling, based at least in part on a clock signal and an enable signal, the source node of the first transistor with a ground voltage source via a switching circuit;
• and
• generating, via circuitry coupled with a drain node of the first transistor and a drain node of the second transistor, an output signal based at least in part on the first input signal, the second input signal, and the coupling of the source node of the first transistor with the ground voltage source via the switching circuit.

A method, comprising:

• receiving, at a gate of a first transistor of a memory device, a first signal from a host device;
• receiving, at a gate of a second transistor of the memory device, a second signal, wherein a source of the second transistor is coupled with a source of the first transistor via a resistor;
• connecting, based at least in part on a clock signal and an enable signal, the source of the first transistor or the source of the second transistor with a ground voltage source via a switching circuit of the memory device;
• and
• generating, via circuitry of the memory device that is coupled with a drain of the first transistor and a drain of the second transistor, a third signal based at least in part on the first signal, the second signal, and the connecting.

An apparatus, comprising:

• a first transistor;
• a second transistor wherein a source node of the second transistor is coupled with a source node of the first transistor via a resistor;
• and
• circuitry configured to cause the apparatus to:
• receive, at a gate of a first transistor, a first input signal;
• receive, at a gate of a second transistor, a second input signal;
• couple, based at least in part on a clock signal and an enable signal, the source node of the first transistor with a ground voltage source via a switching circuit;
• and
• generate an output signal based at least in part on the first input signal, the second input signal, and the coupling of the source node of the first transistor with the ground voltage source via the switching circuit.

An apparatus, comprising:

• an array of memory cells;
• a first transistor;
• a second transistor, wherein a source of the second transistor is coupled with a source of the first transistor via a resistor;
• and
• circuitry configured to cause the apparatus to:
• receive, at a gate of the first transistor, a first signal from a host device;
• receive, at a gate of the second transistor, a second signal;
• connect, based at least in part on a clock signal and an enable signal, the source of the first transistor or the source of the second transistor with a ground voltage source via a switching circuit;
• and
• generate, a third signal based at least in part on the first signal, the second signal, and the connecting.