Cycle-by-cycle reverse current limiting in ACF converters

An active-clamp flyback (ACF) converter comprising:

• a transformer comprising a primary winding and a secondary winding;
• a low-side transistor coupled to the primary winding;
• a clamp capacitor coupled to the primary winding;
• a high-side transistor coupled to the primary winding and the clamp capacitor;
• a current sensor configured to sense a reverse current flowing through the clamp capacitor, the reverse current having a direction from the clamp capacitor to a first terminal of the primary winding;
• and
• a primary controller configured to:
• generate a forward current through the primary winding for a first duration;
• generate a reverse current opposite the forward current through the primary winding for a second duration at an ending of the first duration, wherein an ending of the second duration corresponds to detecting an overcurrent condition at the reverse current or elapsing of a set time duration;
• and
• stop the reverse current for a third duration in response to not detecting an overcurrent condition at the reverse current, the third duration being equal to the set time duration and being after the second duration.

An integrated circuit, comprising:

• a reference terminal configured to receive a reference voltage;
• a voltage sensing terminal configured to be coupled to a clamp capacitor via a sense capacitor and configured to be coupled to the reference terminal via a sense resistor;
• a first control terminal configured to be coupled to a control terminal of a high-side transistor having a current path coupled between the voltage sensing terminal and a first terminal of a primary winding of a transformer;
• a second control terminal configured to be coupled to a control terminal of a low-side transistor having a first current path terminal coupled to the current path of the high-side transistor;
• a comparator having a first input configured to receive a threshold voltage, a second input coupled to the voltage sensing terminal, and an output configured to provide an overcurrent detection signal;
• and
• a primary controller configured to
• generate, by the low-side transistor, a forward current through the primary winding for a first duration;
• generate, by the high-side transistor, a reverse current opposite the forward current through the primary winding for a second duration at an ending of the first duration, wherein an ending of the second duration corresponds to detecting an overcurrent condition at the reverse current or elapsing of a set time duration;
• and
• stop the reverse current for a third duration in response to not detecting an overcurrent condition at the reverse current, the third duration being equal to the set time duration and being after the second duration.