Integrated circuit devices and methods of manufacturing the same

An integrated circuit device comprising:

• a fin shaped active region protruding from a substrate and extending in a first direction;
• a plurality of semiconductor patterns on the fin shaped active region, the plurality of semiconductor patterns being spaced apart from each other in a vertical direction;
• a gate electrode surrounding the plurality of semiconductor patterns and extending in a second direction that is perpendicular to the first direction, the gate electrode comprising:
• a main gate portion extending on an uppermost semiconductor pattern of the plurality of semiconductor patterns in the second direction;
• and
• a plurality of sub-gate portions between the fin shaped active region and lowermost semiconductor pattern of the plurality of semiconductor patterns and between two adjacent ones among the plurality of semiconductor patterns, each sub-gate portion comprising a sub-gate center portion, and sub-gate edge portions comprising opposing end portions of the sub-gate portion, respectively, in the second direction;
• source/drain regions on opposing sides of the plurality of semiconductor patterns, respectively, the source/drain regions being connected to the plurality of semiconductor patterns;
• and
• a plurality of inner spacers between side surfaces of the plurality of sub-gate portions and the source/drain regions,
• wherein, in a horizontal cross-sectional view, a first width of the sub-gate center portion in the first direction is less than a second width of one of the sub-gate edge portions in the first direction, and
• wherein a third width of an uppermost sub-gate portion of the plurality of sub-gate portions in the first direction is less than a fourth width of the main gate portion in the first direction.

An integrated circuit device comprising:

• a substrate including a first region and a second region;
• a first transistor on the first region of the substrate;
• and
• a second transistor on the second region of the substrate,
• wherein each of the first and second transistors comprises:
• a fin shaped active region protruding from the substrate and extending in a first direction;
• a plurality of semiconductor patterns on the fin shaped active region, the plurality of semiconductor patterns being spaced apart from each other in a vertical direction;
• a gate electrode surrounding the plurality of semiconductor patterns and extending in a second direction that is perpendicular to the first direction, the gate electrode comprising:
• a main gate portion extending on an uppermost semiconductor pattern of the plurality of semiconductor patterns in the second direction;
• and
• a plurality of sub-gate portions between the fin shaped active region and a lowermost semiconductor pattern of the plurality of semiconductor patterns and between two adjacent ones among the plurality of semiconductor patterns, each sub-gate portion comprising a sub-gate center portion, and sub-gate edge portions comprising opposing end portions of the sub-gate portion, respectively, in the second direction, wherein, in a horizontal cross-sectional view, a first width of the sub-gate center portion in the first direction is less than a second width of one of the sub-gate edge portions in the first direction;
• and
• source/drain regions on opposing sides of the plurality of semiconductor patterns, respectively, the source/drain regions being connected to the plurality of semiconductor patterns,
• wherein the first transistor further comprises a plurality of inner spacers between side surfaces of the plurality of sub-gate portions and the source/drain regions.