US 11,699,756 B2 · Source/drain diffusion barrier for germanium nMOS transistors

Abstract

Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

Claims20

Dependent claims

An integrated circuit (IC) comprising:

a body of semiconductor material, the semiconductor material comprising germanium;
a gate structure on the body, the gate structure including a gate dielectric and a gate electrode, and the gate structure having a gate-all-around (GAA) configuration on the body of semiconductor material;
a source region and a drain region both adjacent to the body such that the body is between the source and drain regions, at least one of the source region and the drain region including n-type impurity;
a shallow trench isolation (STI) region adjacent the at least one of the source region and the drain region;
and
a layer of insulation material between the at least one of the source region and the drain region and the STI region, wherein the layer of insulation material is distinct from the STI region, and wherein the layer of insulation material comprises silicon, oxygen and carbon.

3 more elements

Dependencies are inferred from the claim text.

Source/drain diffusion barrier for germanium nMOS transistors

Life of this patent

Source/drain diffusion barrier for germanium nMOS transistors

Life of this patent

Abstract

Claims20