Gate structure of vertical FET and method of manufacturing the same

A method for manufacturing a vertical field effect transistor (VFET), the method comprising:

• providing a stack of a bottom source/drain region, a fin structure on the bottom source/drain region, and a gate structure on a side wall of the fin structure, the stack further comprising a bottom spacer between the bottom source/drain region and the gate structure, and the gate structure comprising a gate dielectric layer and a conductor layer sequentially stacked on a sidewall of the fin structure;
• etching the stack from a top surface thereof to remove the gate dielectric layer and the conductor layer, by different depths from the top surface thereof, such that an upper portion of the gate dielectric layer is positioned above a level where a top surface of the conductor layer is positioned, and such that the top surface of the conductor layer is exposed from the gate dielectric layer;
• and
• forming a top source/drain region on the top surface of the fin structure.

A method for manufacturing a vertical field effect transistor (VFET), the method comprising:

• providing a stack of a bottom source/drain region, a fin structure on the bottom source/drain region, and a gate structure on a side wall of the fin structure, the stack further comprising a bottom spacer between the bottom source/drain region and the gate structure, and the gate structure comprising a gate dielectric layer and a conductor layer sequentially stacked on a sidewall of the fin structure;
• etching the stack from a top surface thereof to remove the gate dielectric layer and the conductor layer, by different depths from the top surface thereof, such that an upper portion of the gate dielectric layer is positioned above a level where a top surface of the conductor layer is positioned;
• and
• forming a top source/drain region on the top surface of the fin structure,
• wherein, after etching the stack, the upper portion of the gate dielectric layer is laterally thicker than a lower portion of the gate dielectric layer, on which the conductor layer is formed.