Semiconductor device and method of forming the same
AssigneeSamsung Electronics Co., Ltd.
InventorJun Noh Lee
Life of this patent
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Abstract
A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.
Claims10
A semiconductor device comprising:
- a lower structure;
- a stacked structure on the lower structure and including a first interlayer insulating layer, a second interlayer insulating layer on the first interlayer insulating layer and a cell gate pattern between the first and second interlayer insulating layers;
- a separation structure penetrating through the stacked structure;
- and
- a memory vertical structure penetrating through the stacked structure,
- wherein the memory vertical structure includes a first portion located on a same level as a level of the cell gate pattern and second portions located on a same level as a level of the first and second interlayer insulating layers,
- wherein each of the second portions has a width smaller than a width of the first portion,
- wherein the memory vertical structure includes a first dielectric layer and a second dielectric layer, in contact with each other in the second portions, extended toward the first portion, and spaced apart from each other in the first portion,
- wherein the memory vertical structure further includes a data storage pattern disposed between the first dielectric layer and the second dielectric layer in the first portion,
- wherein the first dielectric layer contacts the cell gate pattern and the first and second insulating layers,
- wherein the cell gate pattern includes an upper surface contacting the second insulating layer, a lower surface contacting the first insulating layer and a first side contacting the first dielectric layer and a second side contacting the separation structure, and
- wherein the first side of the cell gate pattern includes:
- a central protruding portion protruding in a direction toward the first portion of the memory vertical structure in the cell gate pattern;
- a first edge protruding portion adjacent to the first interlayer insulating layer;
- a second edge protruding portion adjacent to the second interlayer insulating layer;
- a first recess portion between the central protruding portion and the first edge protruding portion;
- and
- a second recess portion between the central protruding portion and the first edge protruding portion.
Dependencies are inferred from the claim text.