Semiconductor device with varying numbers of channel layers and method of fabrication thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng-Ting Chung, Kuan-Lun Cheng
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Abstract
A method includes providing a structure having a frontside and a backside, the structure including a substrate, two or more semiconductor channel layers over the substrate and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the semiconductor channel layers, wherein the substrate is at the backside of the structure and the gate structure is at the frontside of the structure; recessing the first S/D feature, thereby exposing a terminal end of one of the semiconductor channel layers; and depositing a dielectric layer on the first S/D feature and covering the exposed terminal end of the one of the semiconductor channel layers.
Claims20
A method, comprising:
- providing a structure having a frontside and a backside, the structure including a substrate, two or more semiconductor channel layers disposed over the substrate and vertically stacked with respect to one another, a first source/drain (S/D) feature and a second S/D feature connected through the semiconductor channel layers therebetween, and a gate structure engaging the semiconductor channel layers, wherein the substrate is at the backside of the structure and the gate structure is at the frontside of the structure;
- recessing the first S/D feature, thereby exposing a terminal end of one of the semiconductor channel layers;
- and
- depositing a dielectric layer on the first S/D feature and covering the exposed terminal end of the one of the semiconductor channel layers.
A method, comprising:
- providing a structure having a frontside and a backside, the structure including a substrate, a semiconductor fin over the substrate, a first source/drain (S/D) feature and a second S/D feature over the semiconductor fin, two or more semiconductor channel layers over the semiconductor fin and connecting the first and second S/D features, and a gate structure engaging the semiconductor channel layers, wherein the substrate is at the backside of the structure and the gate structure is at the frontside of the structure;
- thinning down the structure from the backside of the structure until the semiconductor fin is exposed;
- etching the semiconductor fin from the backside of the structure to form a first trench exposing the first S/D feature;
- recessing the first S/D feature through the first trench, such that a terminal end of a bottommost semiconductor channel layer is exposed in the first trench;
- and
- depositing a dielectric layer in the first trench, wherein the dielectric layer covers the terminal end of the bottommost semiconductor channel layer.
A method, comprising:
- providing a structure having a frontside and a backside, the structure including a substrate, a plurality of semiconductor channel layers vertically stacked with respect to one another and disposed over the substrate, a first epitaxial feature and a second epitaxial feature laterally sandwiching and in physical contact with each of the semiconductor channel layers, and a metal gate stack wrapping around each of the semiconductor channel layers, wherein the substrate is at the backside of the structure;
- etching the substrate from the backside of the structure, thereby exposing the first epitaxial feature;
- recessing the first epitaxial feature, thereby exposing at least an end of a bottommost one of the semiconductor channel layers;
- depositing a dielectric layer in physical contact with the first epitaxial feature and covering the exposed end of the bottommost one of the semiconductor channel layers;
- and
- forming a backside contact in physical contact with the second epitaxial feature.
Dependencies are inferred from the claim text.