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US 11,699,740 B2Granted
Electroless plating method for metal gate fill
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Yi Lee, Chi On Chui
Life of this patent
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Abstract
Embodiments utilize an electro-chemical process to deposit a metal gate electrode in a gate opening in a gate replacement process for a nanosheet FinFET device. Accelerators and suppressors may be used to achieve a bottom-up deposition for a fill material of the metal gate electrode.
Claims20
A method comprising:
- etching a dummy gate of a transistor to remove the dummy gate and form a first opening;
- etching to remove first nanostructures and to extend the first opening, thereby exposing second nanostructures of the transistor;
- depositing a first dielectric layer in the first opening, the first dielectric layer surrounding the second nanostructures;
- depositing a first work function layer in the first opening, the first work function layer surrounding the second nanostructures and the first dielectric layer;
- depositing a glue layer in the first opening, the glue layer surrounding the second nanostructures;
- and
- submerging the first opening in an electro-chemical plating solution to plate a metal into the first opening, the metal filling the first opening, the electro-chemical plating solution comprising accelerators, wherein the accelerators are more densely distributed at a bottom of the first opening than at sidewalls of the first opening during plating the metal.
4 more elements
A method comprising:
- growing epitaxial source/drain regions in a fin recess on either side of a gate;
- performing a replacement gate process, the replacement gate process comprising:
- removing a dummy gate structure between two gate spacers of the gate to form an opening between the two gate spacers;
- depositing a first gate dielectric layer in the opening, the first gate dielectric layer covering a channel region of the gate;
- depositing a work function layer in the opening, the work function layer covering the first gate dielectric layer;
- and
- plating a conductive fill in the opening by an electroless plating process, the electroless plating process plating the conductive fill at a bottom of the opening at a plating rate which is 10 to 25 times greater than at sides of the opening.
4 more elements
A method comprising:
- forming a first nano field effect transistor (nano-FET) gate structure, the forming comprising:
- forming multiple nanostructure channel regions,
- depositing a gate dielectric layer surrounding the multiple nanostructure channel regions,
- depositing a gate work function layer surrounding the gate dielectric layer, and
- depositing a gate fill surrounding the gate work function layer, the depositing the gate fill comprising:
- providing a plating solution in an opening corresponding to the gate fill,
- providing accelerators and suppressors in the plating solution, and
- reducing a metal from the plating solution to deposit the metal at a bottom of the opening;
- and
- forming a first epitaxial source/drain region and a second epitaxial source/drain region disposed on either side of the first nano-FET gate structure, wherein the multiple nanostructure channel regions extend from the first epitaxial source/drain region to the second epitaxial source/drain region, wherein a height to width ratio of the gate fill is between 10:1 and 20:1 in a cross-section through the first epitaxial source/drain region and the second epitaxial source/drain region.
7 more elements
Dependencies are inferred from the claim text.