Integrated circuit with doped low-k side wall spacers for gate spacers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Abstract
Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.
Claims20
A device comprising:
- a gate stack disposed on a substrate, the gate stack having a bottommost surface facing the substrate that is positioned at a first height over the substrate;
- a source/drain feature disposed on the substrate and associated with the gate stack, the source/drain feature including a first-type dopant;
- and
- a first sidewall spacer formed of a low-k dielectric material and disposed on the gate stack, wherein the low-k dielectric material includes a porous low-k dielectric material and a second-type dopant, the second-type being opposite the first-type, the porous low-k dielectric material having a bottommost surface facing the substrate that is positioned at a second height over the substrate, the second height being greater than the first height.
A device comprising
- a first gate stack disposed on a substrate, the first gate stack including a gate dielectric layer;
- a first sidewall spacer disposed along and interfacing with the first gate stack, wherein the first sidewall spacer is formed of a dielectric material that interfaces with the gate dielectric layer and the substrate;
- and
- a second sidewall spacer formed of a low-k dielectric material and disposed along and interfacing with the first sidewall spacer, wherein the low-k dielectric material includes a dielectric material and a dopant selected from the group consisting of an n-type dopant and a p-type dopant, wherein the low-k dielectric material has at least one void therein, and wherein the dopant selected is the n-type dopant.
A device comprising:
- a gate stack disposed on a substrate, the gate stack including a gate dielectric layer and a fill material;
- a first sidewall spacer disposed on a side surface of the gate stack, wherein the first sidewall spacer is formed of a porous low-k dielectric material;
- and
- a second sidewall spacer disposed between the first sidewall spacer and the gate stack such that the second sidewall spacer interfaces with the gate dielectric layer of the gate stack and the substrate, and
- wherein a top surface of the gate dielectric layer, a top surface of the first sidewall spacer and a top surface of the second sidewall spacer each extend to the same height above the substrate, the respective top surfaces of the gate dielectric layer, the first sidewall spacer and the second sidewall spacer facing away from the substrate.
Dependencies are inferred from the claim text.