Semiconductor devices

A method, comprising:

• providing a workpiece including an alternating series of first semiconductor layers and second semiconductor layers disposed directly on a first region and a second region of a semiconductor substrate;
• removing the alternating series of first and second semiconductor layers over the second region of the workpiece except for a bottommost first semiconductor layer;
• forming an epitaxial semiconductor layer on the bottommost first semiconductor layer in the second region;
• patterning the workpiece to form a first fin from the alternating series of first and second semiconductor layers in the first region and a plurality of second fins out of the epitaxial semiconductor layer and the bottommost first semiconductor layer in the second region;
• forming a first dummy gate stack over a first channel region of the first fin and a second dummy gate stack over a second channel region of the plurality of second fins;
• forming a gate spacer over sidewalls of the first dummy gate stack and sidewalls of the second dummy gate stack;
• after the forming of the gate spacer, recessing a first source/drain region of the first fin and a second source/drain region of the plurality of second fins;
• after the recessing, forming a first source/drain feature to couple to the first channel region of the first fin and a second source/drain feature to couple to the second channel region of the plurality of second fins;
• removing the first and second dummy gate stacks;
• removing the first semiconductor layers from the first channel region of the first fin to form first channel members;
• and
• removing the bottommost first semiconductor layer to form second channel members.

A method, comprising:

• providing a workpiece including an alternating series of silicon germanium (SiGe) layers and silicon (Si) layers disposed directly on a first region and a second region of a silicon substrate;
• removing the alternating series of SiGe layers and Si layers over the second region of the workpiece except for a bottommost SiGe layer;
• forming an epitaxial silicon (Si) layer on the bottommost SiGe layer in the second region;
• patterning the workpiece to form a first fin from the alternating series of SiGe layers and Si layers in the first region and a plurality of second fins out of the epitaxial Si layer and the bottommost SiGe layer in the second region;
• forming a first dummy gate stack over a first channel region of the first fin and a second dummy gate stack over a second channel region of the plurality of second fins;
• forming a gate spacer over sidewalls of the first dummy gate stack and sidewalls of the second dummy gate stack;
• after the forming of the gate spacer, recessing a first source/drain region of the first fin and a second source/drain region of the plurality of second fins;
• after the recessing, forming a first source/drain feature to couple to the first channel region of the first fin and a second source/drain feature to couple to the second channel region of the plurality of second fins;
• removing the first and second dummy gate stacks;
• removing the SiGe layers from the first channel region of the first fin to form first channel members;
• and
• removing the bottommost SiGe layer to form second channel members.