Semiconductor devices and methods
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShi Ning Ju, Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang
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Abstract
Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.
Claims20
A method comprising:
- depositing a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer sequentially over a semiconductor substrate;
- etching the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the semiconductor substrate to form a fin, wherein a top surface of the fin has a L-shape in a top-down view;
- etching the first semiconductor layer and the third semiconductor layer to form a first nanostructure from the second semiconductor layer;
- forming a gate dielectric layer around the first nanostructure;
- and
- forming a gate electrode around the gate dielectric layer.
A method comprising:
- depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of first layers that alternate with a plurality of second layers, wherein a material of the plurality of first layers is different from a material of the plurality of second layers;
- patterning the multi-layer stack to form a fin, wherein in a top-down view the fin comprises:
- an active region;
- a first portion of the fin adjacent to a first end of the active region;
- and
- a second portion of the fin adjacent to a second end of the active region, wherein the active region is disposed between the first portion of the fin and the second portion of the fin, the first end of the active region having a first width, and the second end of the active region having a second width different from the first width;
- removing the plurality of first layers to form a plurality of nanostructures from the plurality of second layers;
- and
- depositing a gate electrode around each of the plurality of nano structures.
A device comprising:
- a plurality of channel regions over a substrate;
- a gate dielectric surrounding each of the plurality of channel regions, wherein the plurality of channel regions is vertically stacked;
- a gate electrode around the gate dielectric;
- a first source/drain region on a first side of the gate electrode;
- and
- a second source/drain region on a second side of the gate electrode, wherein a first channel width of each of the plurality of channel regions on the first side is larger than a second channel width of each of the plurality of channel regions on the second side, wherein the first channel width and the second channel width are measured along directions parallel to each other.
Dependencies are inferred from the claim text.