Semiconductor device having an alignment layer with mask pits

A semiconductor device, comprising:

• first trenches extending from a first surface into a semiconductor layer;
• an alignment layer on the first surface and comprising mask pits formed in the alignment layer in a vertical projection of the first trenches, wherein sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the first trenches;
• and
• a gate trench formed in a mesa section of the semiconductor layer between the first trenches.

A semiconductor device, comprising:

• a plurality of transistor cells each of which comprises:
• a field electrode structure or a portion of a field electrode structure extending from a first surface into a semiconductor portion;
• at least one doped semiconductor region formed in a mesa section of the semiconductor portion;
• and
• a gate structure formed in the mesa section and comprising a gate electrode insulated against the mesa section by a gate dielectric;
• an interlayer dielectric on the first surface and the field electrode structures;
• and
• a first load electrode on the interlayer dielectric,
• wherein the interlayer dielectric comprises an alignment layer and a dielectric layer,
• wherein the alignment layer has mask pits in a vertical projection of at least portions of the field electrode structures,
• wherein sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures,
• wherein between neighboring mask pits, an opening in the alignment layer extends in a vertical direction through the alignment layer,
• wherein the openings are in the vertical projection of the gate structures,
• wherein the dielectric layer fills the mask pits and the openings.