US 11,699,701 B2 · Semiconductor device

Abstract

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Claims20

Dependent claims

A device, comprising:

a substrate having a semiconductor fin;
a first dielectric layer disposed on and in contact with a portion of the semiconductor fin;
a second dielectric layer disposed on and in contact with another portion of the semiconductor fin, wherein an area of the first dielectric layer in contact with the portion of the semiconductor fin is greater than an area of the second dielectric layer in contact with the another portion of the semiconductor fin, and a thickness of the first dielectric layer is different than a thickness of the second dielectric layer;
a first gate disposed on the first dielectric layer and across the semiconductor fin, and in contact with an upper surface of the first dielectric layer;
a second gate disposed on the second dielectric layer and across the semiconductor fin, wherein the first dielectric layer is in contact with side surfaces of the second gate, and a width of the second gate is greater than a width of the first gate.

2 more elements

A device, comprising:

a substrate having a semiconductor fin;
a first gate disposed on the substrate across the semiconductor fin;
a second gate disposed on the substrate across the semiconductor fin, wherein a width and a height of the first gate is different than a width and a height of the second gate;
interlayer dielectric layers located on the substrate over the semiconductor fin and surrounding the first gate and the second gate, wherein a top surface of the interlayer dielectric layers is coplanar with top surfaces of the first gate and the second gate;
a first dielectric layer located below the first gate and the interlayer dielectric layers, and in contact with the first gate and the interlayer dielectric layers, wherein the first dielectric layer is in contact with side surfaces of the second gate;
a second dielectric layer located below the second gate and in contact with the semiconductor fin, wherein the second dielectric layer is confined in an area overlapped with the second gate, and a thickness of the second dielectric layer is different than a thickness of the first dielectric layer, and wherein a bottom surface of the second dielectric layer is located at a level below a bottom surface of the first dielectric layer;
and
a plurality of insulators disposed on the substrate and located below and in contact with the first dielectric layer, the second dielectric layer and the second gate,
wherein the plurality of insulators is in contact with a first portion of a bottom surface of the second gate, and the second dielectric layer is in contact with a second portion of the bottom surface of the second gate.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims20