Multi-function threshold gate with adaptive threshold and stacked planar ferroelectric capacitors

An apparatus comprising:

• a first transistor, the first transistor having a first source region and a first drain region, and a first gate, wherein the first gate is controllable by a first control;
• a second transistor, the second transistor having a second source region and a second drain region, and a second gate, wherein the second gate is controllable by a second control;
• a first via is coupled to the first source region;
• a second via is coupled to the first drain region;
• a first metal layer over the first via, the first metal layer that extends along an x-plane;
• a second etch stop layer over the first metal layer;
• a third via, over the first metal layer, and etched through the second etch stop layer, the third via in direct connection to the first metal layer;
• a second metal layer that extends along the x-plane, wherein the second metal layer is above the first metal layer, and wherein the second metal layer couples the third via;
• an interlayer dielectric between the first metal layer and the second metal layer;
• a first pedestal filled with metal, wherein the first pedestal is coupled to the second metal layer;
• a first plurality of layers to form a first planar capacitor, wherein the first plurality of layers includes a first ferroelectric dielectric material, wherein a first layer of the first plurality of layers is in contact with a top portion of the first pedestal, and wherein a second layer of the first plurality of layers is coupled to a first input line;
• a fourth via in direct connection to the second metal layer;
• a third metal layer over the fourth via, wherein the first plurality of layers is between the second metal layer and the third metal layer;
• a second pedestal filled with metal, wherein the second pedestal is coupled to the third metal layer;
• and
• a second plurality of layers to form a second planar capacitor, wherein the second plurality of layers includes a second ferroelectric dielectric material, wherein a first layer of the second plurality of layers is in direct contact with a top portion of the second pedestal, and wherein a second layer of the second plurality of layers is coupled to a second input line.

A system comprising:

• a memory to store one or more instructions;
• a processor circuitry to execute the one or more instructions;
• and
• a communication device to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes a capacitive input circuit and a configuration circuit, and wherein the capacitive input circuit comprises:
• a first metal layer that extends along an x-plane;
• a second metal layer that extends along the x-plane, wherein the second metal layer is above the first metal layer;
• a first via that extends along a y-plane, wherein the y-plane is orthogonal to the x-plane, and wherein the first via couples the first metal layer with the second metal layer;
• a second via that extends along the y-plane, wherein the second via couples the second metal layer, wherein the second via is above the first via;
• a first pedestal on the first metal layer, wherein the first pedestal is laterally offset from the first via;
• a second pedestal on the second metal layer, wherein the second pedestal is laterally offset from the second via;
• a summing node coupled to the first via;
• a first input line that extends along a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane;
• a second input line that extends along the z-plane;
• a first planar stack of materials including a first ferroelectric dielectric material, wherein the first planar stack of materials has a top electrode and a bottom electrode, wherein the first ferroelectric dielectric material is between the top electrode and the bottom electrode, wherein the bottom electrode is on the first pedestal, and wherein the first input line is on the top electrode;
• a second planar stack of materials including a second ferroelectric dielectric material, wherein the second planar stack of materials has a top electrode and a bottom electrode, wherein the second ferroelectric dielectric material is between the top electrode of the second planar stack of materials and the bottom electrode and the second planar stack of materials, wherein the bottom electrode is on the second pedestal, and wherein the second input line on the top electrode of the second planar stack of materials;
• a pull-up device coupled to the summing node and a power supply rail;
• and
• a pull-down device coupled to the summing node and a ground.