Memory device

A memory device comprising:

• a first chip including a first area and a third area;
• and
• a second chip including a second area disposed in a position corresponding to a position of the first area, and a fourth area disposed in a position corresponding to a position of the third area,
• wherein a first metal pad disposed on an uppermost metal layer of the first area and a second metal pad disposed on an uppermost metal layer of the second area are connected to each other, the first metal pad being connected to a memory cell array of the first chip, and the second metal pad being connected to a peripheral circuit of the second chip, and
• wherein a third metal pad disposed on an uppermost metal layer of the third area and a fourth metal pad disposed on an uppermost metal layer of the fourth area are connected to each other, the third metal pad being not connected to the memory cell array of the first chip, and the fourth metal pad being connected to the peripheral circuit of the second chip, and
• wherein the fourth metal pad forms a power routing wire used for supplying power to the peripheral circuit of the second chip.

A memory device comprising:

• a first chip including a first metal pad in a first area and a second metal pad and a third metal pad in a second area;
• and
• a second chip including a fourth metal pad in a third area corresponding to the first area and a fifth metal pad and a sixth metal pad in a fourth area corresponding to the second area,
• wherein the first metal pad and the fourth metal pad are connected vertically to each other, the first metal pad being connected to a memory cell array of the first chip, and the fourth metal pad being connected to a peripheral circuit of the second chip,
• wherein the second metal pad and the fifth metal pad are connected vertically to each other, the second metal pad being connected to the memory cell array of the first chip, and the fifth metal pad being connected to the peripheral circuit of the second chip,
• wherein the third metal pad and the sixth metal pad are connected vertically to each other, the third metal pad being not connected to the memory cell array of the first chip, and the sixth metal pad being connected to the peripheral circuit of the second chip, and
• wherein the third metal pad and the sixth metal pad are used as a routing wire for supplying power to the peripheral circuit of the second chip.