Semiconductor package

A semiconductor package, comprising:

• a substrate including a substrate pad;
• a first lower stack on the substrate, the first lower stack including a plurality of first lower semiconductor chips stacked on each other;
• a redistribution substrate on the first lower stack, the redistribution substrate including at least one redistribution pad;
• a first upper stack on the redistribution substrate, the first upper stack including a plurality of first upper semiconductor chips stacked in a cascade formation, each of the first upper semiconductor chips including a first upper pad exposed on one side edge at a top surface thereof;
• a second upper stack on the redistribution substrate and horizontally spaced apart from the first upper stack, the second upper stack including a plurality of second upper semiconductor chips stacked in a cascade formation, each of the second upper semiconductor chips including a second upper pad exposed on one side edge at a top surface thereof;
• a first upper connector electrically connecting the first upper pad to the redistribution substrate;
• and
• a second upper connector electrically connecting the second upper pad to the redistribution substrate,
• wherein the at least one redistribution pad is on a top surface of the redistribution substrate, the top surface of the redistribution substrate being a surface on which the first upper stack and the second upper stack are provided.

A semiconductor package, comprising:

• a substrate;
• a first lower stack on the substrate, the first lower stack including a plurality of first lower semiconductor chips stacked on each other;
• a controller on the substrate and horizontally spaced apart from the first lower stack;
• a second lower stack on the substrate and horizontally spaced apart from the first lower stack across the controller;
• a redistribution substrate on the first lower stack, the controller, and the second lower stack, the redistribution substrate including a redistribution pattern;
• a redistribution adhesive layer between a bottom surface of the redistribution substrate and the first and second lower stacks;
• a redistribution connector on the substrate, the redistribution connector electrically connecting the substrate to the redistribution substrate;
• a first upper stack on the redistribution substrate, the first upper stack including a plurality of first upper semiconductor chips stacked in a cascade formation;
• a first upper connector on the redistribution substrate, the first upper connector electrically connecting the redistribution substrate to the first upper semiconductor chips;
• a second upper stack on the redistribution substrate and horizontally spaced apart from the first upper stack, the second upper stack including a plurality of second upper semiconductor chips stacked in a cascade formation;
• a second upper connector on the redistribution substrate, the second upper connector electrically connecting the redistribution substrate to the second upper semiconductor chips;
• and
• a molding layer on the substrate, the molding layer covering the redistribution substrate, the first upper stack, and the second upper stack.