Semiconductor package device with integrated inductor and manufacturing method thereof

A method, comprising:

• forming an interconnect structure over a substrate, the interconnect structure comprising a plurality of metallization layers forming an interconnection path and an inductor electrically isolated from the interconnection path, wherein the plurality of metallization layers comprise:
• first metal features in an inductor zone to form a coil of the inductor and comprise a magnetic region extending within the coil of the inductor, wherein the coil comprises first conductive vias in a first metallization layer, second conductive vias in a second metallization layer over the first metallization layer, and a third conductive via in a third metallization layer between the first conductive vias and the second conductive vias;
• and
• second metal features arranged outside the inductor zone, the second metal features including a plurality of connecting metal vias parallel to each other in the first metallization layer or the second metallization layer, wherein each of the connecting metal vias is electrically isolated from the inductor zone, and has an upper surface and a bottom surface aligned with an upper surface and a bottom surface, respectively, of each of the first or second conductive vias.

A method, comprising:

• forming an interconnect structure over a semiconductor substrate, the forming comprising:
• forming an inductor in an inductor zone, the inductor comprising a coil and a magnetic core wrapped around by the coil, the forming of the inductor comprising:
• depositing first metal lines in the interconnect structure;
• depositing the magnetic core over the first metal lines;
• depositing metal vias laterally spaced apart from the magnetic core and electrically connected to the first metal lines, wherein the metal vias comprises first metal vias arranged in a first metallization layer of the interconnect structure, second metal vias arranged in a second metallization layer of the interconnect structure over the first metallization layer, and a third metal via between the first metallization layer and the second metallization layer;
• and
• depositing second metal lines over the metal vias and electrically insulated from the magnetic core;
• depositing a connecting metal line adjacent to and on the outside of the inductor zone, the connecting metal line being electrical isolated from the inductor zone and having an upper surface and a bottom surface aligned with an upper surface and a bottom surface, respectively, of the magnetic core;
• and
• depositing a plurality of connecting metal vias parallel to each other and electrically coupled to the bottom surface or the upper surface of the connecting metal line, wherein each of the connecting metal vias is electrically isolated from the inductor zone, and has an upper surface and a bottom surface aligned with an upper surface and a bottom surface, respectively, of each of the first or second metal vias;
• and
• electrically coupling a first semiconductor die to the interconnect structure.