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US 11,699,662 B2Granted
Face-to-face dies with probe pads for pre-assembly testing
AssigneeNVIDIA Corporation
InventorsJoseph Greco, Joseph Minacapelli
Life of this patent
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Abstract
In accordance with the disclosure, one or both semiconductor dies in a face-to-face arrangement may include a probe pad layer formed on a face of the die to allow the die to be individually tested prior to assembly of the dies. Thus, faulty dies may be discarded individually so they are not included in a composite semiconductor device, thereby increasing device yields. The probe pad layer also allows dies to be matched so that a composite semiconductor device achieves desired performance, which may further increase device yields. In some embodiments, the probe pads of the probe pad layer formed on the face of the die may be used to individually test the die, and may remain inactive, or inert, during operation of the composite semiconductor device.
Claims20
A semiconductor device comprising:
- a first semiconductor die including,
- a semiconductor substrate,
- a first logic circuit comprised in the semiconductor substrate,
- a layer of probe pads,
- a metallization region, and
- a layer of inter-die interface pads on a frontside of the first semiconductor die, and
- a second semiconductor die including a semiconductor substrate comprising a second logic circuit;
- wherein a face-to-face arrangement includes the frontside of the first semiconductor die mounted to a frontside of the semiconductor die;
- wherein a layer of interface terminals of the first semiconductor die is configured as a first signal communications interface to the first semiconductor die and the second semiconductor die;
- wherein the layer of probe pads of the first semiconductor die is disposed between the semiconductor substrate of the second semiconductor die and the metallization region of the first semiconductor die, the layer of probe pads used to test the first logic circuit through the metallization region of the first semiconductor die prior to forming the face-to-face arrangement;
- and
- wherein the layer of inter-die interface pad layer is formed over the layer of probe pads and are configured as a second signal communications interface between the first logic circuit of the first semiconductor die and the second logic circuit of the second semiconductor die.
9 more elements
A semiconductor device comprising:
- a first semiconductor die including,
- a first logic circuit,
- a semiconductor substrate, and
- a layer of interface terminals on a backside of the first semiconductor die;
- and
- a second semiconductor die including,
- a semiconductor substrate,
- a second logic circuit comprised in the semiconductor substrate,
- a metallization region,
- a layer of inter-die interface pads on a frontside of the second semiconductor die, and
- a probe pad layer;
- wherein a face-to-face arrangement includes a frontside of the first semiconductor die mounted to the frontside of the second semiconductor die;
- wherein the layer of interface terminals of the first semiconductor die is configured as a first signal communications interface to the first semiconductor die and the second semiconductor die;
- wherein the layer of probe pads of the second semiconductor die is disposed between the metallization region of the second semiconductor die and the semiconductor substrate of the first semiconductor die, the layer of probe pads is used to test the second logic circuit through at least one metallization layer of the metallization region of the second semiconductor die prior to forming the face-to-face arrangement;
- and
- wherein the layer of inter-die interface pads is formed over the layer of probe pads and are configured as a second signal communications interface between the first logic circuit of the first semiconductor die and the second logic circuit of the second semiconductor die.
13 more elements
A semiconductor package comprising:
- a first semiconductor die including,
- a semiconductor substrate,
- a processing unit,
- a layer of probe pads,
- a metallization region, and
- a layer of inter-die interface pads on a frontside of the first semiconductor die;
- a second semiconductor die including,
- a semiconductor substrate, and
- a processing unit;
- and
- package signal terminals to provide signals to a composite logic circuit that includes the processing unit in the first semiconductor die and the processing unit in the second semiconductor die;
- wherein a face-to-face arrangement includes the frontside of the first semiconductor die mounted to a frontside of the second semiconductor die;
- wherein the layer of probe pads of the first semiconductor die is disposed between the metallization region of the first semiconductor die and the semiconductor substrate of the second semiconductor die, the layer of probe pads used to test the processing unit in the first semiconductor die prior to forming the face-to-face arrangement;
- and
- wherein the layer of inter-die interface pads is formed over the layer of probe pads of the first semiconductor die and are configured as a signal communications interface between the processing unit of the first semiconductor die and the processing unit of the second semiconductor die to form the composite logic circuit.
12 more elements
Dependencies are inferred from the claim text.