Semiconductor integrated circuit device

A semiconductor integrated circuit device, comprising:

• a chip;
• a core region provided on the chip;
• an IO region provided between the core region and a periphery of the chip on the chip;
• an IO cell row placed in the IO region, constituted by a plurality of IO cells arranged in a first direction, the first direction being a direction along the periphery of the chip;
• and
• power supply lines placed in the IO region, extending in the first direction, wherein
• the plurality of IO cells each have a low power supply voltage region and a high power supply voltage region separated in a second direction perpendicular to the first direction, the low power supply voltage region being located closer to the core region,
• the power supply lines includes:
• a first power supply line extending in the first direction in the low power supply voltage region, for supply of a first power supply voltage,
• a second power supply line extending in the first direction in the low power supply voltage region and located father from the core region than the first power supply line, for supply of a second power supply voltage, the second power supply voltage being lower than the first power supply voltage,
• a third power supply line extending in the first direction in the high power supply voltage region and located farther from the core region than the second power supply line, for supply of the second power supply voltage, and
• a fourth power supply line extending in the first direction in the high power supply voltage region, and located farther from the core region than the second power line and nearer the core region than the third power supply line, for supply of a third power supply voltage, the third power voltage being higher than the first power supply voltage,
• the first, second, third and fourth power supply lines are provided in a first wiring layer,
• the first power supply line has a first portion protruding from the low power supply voltage region to the core region, and
• a first IO cell as a signal IO cell among the plurality of IO cells has a first reinforcing line extending in the second direction in a second wiring layer located above the first wiring layer, for mutually connecting the second and third power supply lines.