Staircase structure in three-dimensional memory device and method for forming the same

A three-dimensional (3D) memory device, comprising:

• a memory array structure;
• and
• a staircase structure comprising a plurality of stairs extending along a first lateral direction, the plurality of stairs comprising a stair comprising a conductor portion on a top surface of the stair and a dielectric portion at a same level and in contact with the conductor portion, the conduction portion being electrically connected to the memory array structure, wherein
• along a second lateral direction perpendicular to the first lateral direction, a width of the conductor portion decreases.

A method for forming a staircase structure of a three-dimensional (3D) memory device, comprising:

• forming interleaved a plurality of sacrificial layers and a plurality of dielectric layers, each of the sacrificial layers comprises a first sacrificial layer and a second sacrificial layer in contact with each other, each of the dielectric layers comprises a first dielectric layer and a second dielectric layer in contact with each other;
• forming a plurality of stairs comprising the interleaved plurality of first sacrificial layers and plurality of first dielectric layers;
• forming a sacrificial portion in the first sacrificial layer corresponding to at least one of the stairs, the sacrificial portion being at a top surface of the respective stair;
• removing, by a same etching process, the second sacrificial layers and the sacrificial portion to respectively form a plurality of lateral recesses and a lateral recess portion;
• and
• forming a plurality of conductor layers in the lateral recesses, and a conductor portion in the lateral recess portion and in contact with a respective one of the conductor layers.