Three-dimensional memory devices having a plurality of NAND strings located between a substrate and a single crystalline silicon layer

A three-dimensional (3D) memory device, comprising:

• a memory string;
• an array interconnect layer, comprising:
• a word line via;
• and
• a bit line contact in direct contact with an upper end of the memory string;
• a peripheral interconnect layer in direct contact with the array interconnect layer;
• a peripheral device in direct contact with the peripheral interconnect layer;
• a crystalline semiconductor layer, wherein the peripheral device is in direct contact with a first surface of the crystalline semiconductor layer;
• and
• a back-end-of-line (BEOL) interconnect layer in direct contact with a second surface of the crystalline semiconductor layer, wherein the first and second surfaces are on opposite sides of the crystalline semiconductor layer.

A three-dimensional (3D) memory device, comprising:

• an alternating conductor/dielectric stack;
• a plurality of word line contacts, wherein each word line contact comprises:
• an upper end;
• and
• a lower end in direct contact with a corresponding conductor layer of the conductor/dielectric stack;
• an array interconnect in direct contact with the upper end of the each word line contact;
• a peripheral interconnect in direct contact with the array interconnect;
• a peripheral device above the alternating conductor/dielectric stack and in direct contact with the peripheral interconnect;
• a single crystalline silicon layer above and in direct contact with the peripheral device;
• a back-end-of-line (BEOL) interconnect layer above and in direct contact with the single crystalline silicon layer;
• and
• a plurality of memory strings extending vertically through the alternating conductor/dielectric stack and disposed between a substrate and the single crystalline silicon layer, wherein each memory string comprises:
• a semiconductor channel extending vertically through the alternating conductor/dielectric stack;
• a tunneling layer between the alternating conductor/dielectric stack and the semiconductor channel;
• and
• a storage layer between the tunneling aye and the alternating conductor/dielectric stack.