Transistor and fabrication method thereof

A transistor, comprising:

• a gate;
• a channel layer, overlapping the gate;
• a gate insulation layer, disposed between the gate and the channel layer;
• a passivation layer, disposed over the gate insulation layer;
• a first conductive via, disposed in the passivation layer and overlapping the channel layer;
• a second conductive via, disposed in the passivation layer and overlapping the channel layer, wherein the second conductive via is in contact with the channel layer;
• and
• a liner comprising:
• an insulation region, disposed over the passivation layer and on sidewalls of the first conductive via;
• and
• a conductive region, disposed under a bottom of the first conductive via, wherein the first conductive via is electrically connected with the channel layer through the conductive region, and the conductive region and the insulation region are integrally formed.

A transistor, comprising:

• a gate;
• a gate insulation layer, disposed over the gate;
• a channel layer, disposed over the gate insulation layer;
• a first passivation layer, disposed over the gate insulation layer;
• a second passivation layer, embedded in the first passivation layer, wherein the second passivation layer contains hydrogen;
• a first signal line, embedded in the second passivation layer, wherein the channel layer comprises an n-type doped region disposed at the junction between the channel layer and the second passivation layer and between the channel layer and the first signal line;
• a second signal line, connected with the channel layer.