Fan-out interconnect integration processes and structures
AssigneeApplied Materials, Inc.
InventorsRichard W. Plavidal, Albert Lan
Life of this patent
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Abstract
Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.
Claims20
A method of forming a fan-out interconnect structure, the method comprising:
- forming a semiconductor active device structure overlying a first substrate, wherein the semiconductor active device structure comprises first conductive contacts protruding from one or more metallization layers disposed in dielectric material overlying a semiconductor active device layer, wherein the one or more metallization layers form an initial interconnect layer for active devices in the active device laver;
- forming an interconnect structure overlying a second substrate, wherein the second substrate comprises a fan-out interconnect substrate, the interconnect structure comprises second conductive contacts, the interconnect structure comprises a global interconnect layer for the active devices in the active device layer, and the global interconnect layer connects to the fan-out interconnect substrate without a redistribution layer between the global interconnect layer and the fan-out interconnect substrate;
- and
- joining the first substrate with the second substrate, wherein the joining comprises coupling the first conductive contacts with the second conductive contacts, and wherein the interconnect structure extends beyond lateral dimensions of the semiconductor active device structure.
A method of forming an interconnect structure, the method comprising:
- forming a reverse interconnect structure for one or more active devices over a fan-out interconnect substrate, wherein the reverse interconnect structure comprises a conductive material formed within a plurality of layers of dielectric material to form a global interconnect layer for active devices in an active device layer of a first semiconductor active device, and the global interconnect layer connects to the fan-out interconnect substrate without a redistribution layer between the global interconnect layer and the fan-out interconnect substrate;
- forming a plurality of vias along a first surface of the reverse interconnect structure opposite a second surface adjacent the fan-out interconnect substrate, wherein the vias provide access to the conductive material;
- lining each via of the plurality of vias with the conductive material;
- at least partially filling each via with a conductive filler material;
- positioning a plurality of conductive extensions of the first semiconductor active device within a subset of the plurality of vias, the conductive extensions protruding from one or more metallization layers disposed in dielectric material overlying a semiconductor active device layer of the first semiconductor active device, wherein the one or more metallization layers form an initial interconnect layer for the active devices in the active device layer;
- and
- melting the conductive filler material to electrically couple the conductive extensions of the first semiconductor active device with the conductive material of the reverse interconnect structure.
A method of forming an interconnect structure, the method comprising:
- forming a reverse interconnect structure for one or more active devices over a fan-out interconnect substrate, wherein the reverse interconnect structure comprises a conductive material formed within a plurality of layers of dielectric material to form a global interconnect layer for active devices in an active device layer of a first semiconductor active device that is separate from the reverse interconnect structure, and the global interconnect layer connects to the fan-out interconnect substrate without a redistribution layer between the global interconnect layer and the fan-out interconnect substrate;
- and
- forming a plurality of contact landings along a first surface of the reverse interconnect structure opposite a second surface adjacent the fan-out interconnect substrate, wherein the contact landings provide access to the conductive material, and wherein each contact landing of the plurality of contact landings is sized larger than a corresponding conductive extension of one or more semiconductor active device structures.
Dependencies are inferred from the claim text.