Integrated circuit structure with capacitor electrodes in different ILD layers, and related methods

An integrated circuit (IC) structure, comprising:

• a first metal wiring level including:
• a first inter-level dielectric (ILD) layer having a top surface,
• a first rounded electrode within the first ILD layer, and having a top surface substantially coplanar with the top surface of the first ILD layer, and
• a barrier film on the top surface of the first ILD layer of the first metal wiring level, wherein a portion of the barrier film on the top surface of the first rounded electrode defines a capacitor dielectric film;
• and
• a second metal wiring level including:
• a second ILD layer on a first portion of the barrier film,
• a first via within the second ILD layer, and horizontally distal to the capacitor dielectric film, and
• a second rounded electrode within the second ILD layer and on a second portion of the barrier film, wherein the second rounded electrode is horizontally distal to the first via in the second ILD layer, and the second portion of the barrier film defines a capacitor dielectric region vertically between the first rounded electrode and the second rounded electrode.

A method of forming an integrated circuit (IC) structure, the method comprising:

• forming a first metal wiring level including a first rounded electrode within a first inter-level dielectric (ILD) layer, wherein a top surface of the first rounded electrode is substantially coplanar with a top surface of the first ILD layer;
• forming a capacitor dielectric film on a top surface of the first rounded electrode;
• forming a second metal wiring level including a second ILD layer over the first ILD layer;
• forming a second rounded electrode within the second ILD layer of the second metal wiring level over the capacitor dielectric film, wherein forming the second rounded electrode causes the capacitor dielectric film to be vertically between the first rounded electrode and the second rounded electrode;
• and
• forming a via within the second ILD layer of the second metal wiring level, wherein the via is horizontally distal to the capacitor dielectric film and the second rounded electrode.