Semiconductor device having wiring substrate with lead-out wirings

A semiconductor device comprising:

• a semiconductor chip having a first surface and a plurality of electrode terminals arranged on the first surface;
• and
• a wiring substrate on which the semiconductor chip is mounted,
• wherein the wiring substrate includes:
• a first wiring layer having a plurality of pads connected to the plurality of electrode terminals, respectively;
• a second wiring layer having a plurality of wirings electrically connected to the plurality of pads, respectively, and a plurality of via-lands connected to the plurality of wirings, respectively;
• and
• a plurality of via-wirings electrically connecting the plurality of pads on the first wiring layer with the plurality of via-lands on the second wiring layer, respectively,
• wherein, in a perspective plan view seeing the wiring substrate from the semiconductor chip, each of the first wiring layer and the second wiring layer includes:
• a first region overlapping with the semiconductor chip;
• and
• a second region not overlapping with the semiconductor chip,
• wherein each of the plurality of pads is arranged in the first region of the first wiring layer,
• wherein each of the plurality of wirings is arranged in each of the first region on the second wiring layer and the second region on the second wiring layer such that each of the plurality of wirings straddles a first side of the semiconductor chip in the perspective plan view,
• wherein the plurality of pads includes:
• a plurality of first-row pads arranged along the first side of the semiconductor chip in the perspective plan view and arranged at a position closest to the first side;
• and
• a plurality of second-row pads arranged along the first side of the semiconductor chip in the perspective plan view and arranged at a position second closest to the first side,
• wherein the plurality of via-lands includes:
• a plurality of first-row via-lands connected to the plurality of first-row pads, respectively;
• and
• a plurality of second-row via-lands connected to the plurality of second-row pads, respectively,
• a plurality of first via-lands arranged such that a center of each of the plurality of first via-lands is shifted in a direction away from the first side of the semiconductor chip than a position overlapping with a center of the corresponding first-row pad in the perspective plan view, and
• a plurality of second via-lands arranged such that a center of each of the plurality of second via-lands is arranged at a position closer to the first side of the semiconductor chip than the first via-land in the perspective plan view, and
• wherein, in the perspective plan view, the plurality of first via-lands and the plurality of second via-lands are alternately arranged in a first direction along the first side of the semiconductor chip.