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US 11,699,644 B2Granted
Organic mold interconnects in shielded interconnects frames for integrated-circuit packages
AssigneeIntel Corporation
InventorsJiun Hann Sir, Eng Huat Goh, Poh Boon Khoo
Life of this patent
Estimating the term…
Abstract
A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.
Claims16
An integrated-circuit package assembly, comprising:
- an integrated-circuit (IC) package substrate, including a die side and a land side;
- a plurality of interconnects located at a periphery of the package substrate, including:
- an input/output interconnect that extends at least the height of the IC package land side to a redistribution layer near the IC package die side, wherein the input/output interconnect is shielded by a ground (Vss) annulus;
- a power interconnect that extends at least the height of the IC package land side to the redistribution layer near the IC package die side, wherein the power interconnect is shielded by a ground (Vss) annulus;
- wherein the redistribution layer is coupled to each of the IC package substrate, the input/output interconnect and the power interconnect.
2 more elements
An integrated-circuit package assembly, comprising:
- an integrated-circuit (IC) package substrate, including a die side and a land side;
- a plurality of interconnects located at a periphery of the package substrate, including:
- an input/output interconnect that extends at least the height of the IC package land side to a redistribution layer near the IC package die side, wherein the input/output interconnect is shielded by a ground (Vss) annulus;
- a power interconnect that extends at least the height of the IC package land side to the redistribution layer near the IC package die side, wherein the power interconnect is shielded by a ground (Vss) annulus;
- an intermediate-height interconnect that extends from the IC package land side to an insert redistribution layer;
- and
- the redistribution layer, wherein the redistribution layer is coupled to the insert redistribution layer, and to each of the IC package substrate, the input/output interconnect and the power interconnect.
4 more elements
A computing system comprising:
- an integrated-circuit die on a die side of an integrated-circuit package substrate;
- a plurality of interconnects located at a periphery of the package substrate, including:
- an input/output interconnect that extends at least the height of the IC package land side to a redistribution layer near the IC package die side, wherein the input/output interconnect is shielded by a ground (Vss) annulus;
- a power interconnect that extends at least the height of the IC package land side to the redistribution layer near the IC package die side, wherein the power interconnect is shielded by a ground (Vss) annulus;
- wherein the redistribution layer is coupled to each of the IC package substrate, the input/output interconnect and the power interconnect;
- wherein the IC package substrate is coupled to a printed wiring board at the land side;
- and
- wherein the IC die is part of a chipset.
5 more elements
Dependencies are inferred from the claim text.