Semiconductor package including redistributed layer and method for fabrication therefor

A semiconductor package comprising:

• a redistribution layer;
• a semiconductor chip electrically connected to the redistribution layer, and disposed on an upper surface of the redistribution layer;
• a plurality of inner solder balls electrically connected to the redistribution layer, and disposed on the upper surface of the redistribution layer;
• an interposer electrically connected to the plurality of inner solder balls, and disposed on an upper surface of the plurality of inner solder balls;
• an encapsulant layer encapsulating the semiconductor chip, side surfaces of the redistribution layer and a bottom surface and a portion of the upper surface of the redistribution layer under the interposer;
• and
• an underfill layer filling a space between a lower surface of the interposer and an upper surface of the encapsulant layer,
• wherein the encapsulant layer includes a side surface encapsulant region surrounding the side surfaces of the redistribution layer, a first region surrounding the semiconductor chip and covering the upper surface of the redistribution layer, and a lower surface encapsulant region covering the bottom surface of the redistribution layer,
• wherein the side surface encapsulant region and the first region are continuously integrated with each other without a boundary therebetween and integrally formed through a single process,
• wherein the underfill layer contacts the lower surface of the interposer, the upper surface of the encapsulant layer, an upper surface of the semiconductor chip, and side surfaces of the plurality of inner solder balls, and
• wherein upper portions of the plurality of inner solder balls are surrounded by the underfill layer and lower portions of the plurality of inner solder balls are surrounded by the encapsulant layer and contact the encapsulant layer.

A semiconductor package comprising:

• a redistribution layer including a plurality of dielectric layers and a plurality of metal distribution lines;
• a semiconductor chip disposed on an upper surface of the redistribution layer;
• a connection structure between the redistribution layer and the semiconductor chip;
• a plurality of inner solder balls disposed on the upper surface of the redistribution layer, the plurality of inner solder balls being spaced apart from the semiconductor chip;
• an encapsulant layer encapsulating the semiconductor chip, the plurality of inner solder balls, and a side surface and a portion of the upper surface of the redistribution layer;
• an interposer disposed on the semiconductor chip, the plurality of inner solder balls, and the encapsulant layer;
• an underfill between the semiconductor chip and the interposer;
• and
• a plurality of external solder balls disposed on a bottom surface of the redistribution layer,
• wherein the underfill contacts a lower surface of the interposer, an upper surface of the encapsulant layer, an upper surface of the semiconductor chip, and side surfaces of the plurality of inner solder balls,
• wherein the encapsulant layer includes a side surface encapsulant region surrounding the side surfaces of the redistribution layer, and a first region surrounding the semiconductor chip and covering the upper surface of the redistribution layer,
• wherein the side surface encapsulant region and the first region are continuously integrated with each other without a boundary therebetween and integrally formed through a single process, and
• wherein upper portions of the plurality of inner solder balls are surrounded by the underfill and lower portions of the plurality of inner solder balls are surrounded by the encapsulant layer and contact the encapsulant layer.