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US 11,699,627 B2Granted
DMOS FET chip scale package and method of making the same
AssigneeAlpha and Omega Semiconductor International LP
InventorsYan Xun Xue, Long-Ching Wang, Hongyong Xue, Madhur Bobde, Zhiqiang Niu, Jun Lu
Life of this patent
Estimating the term…
Abstract
A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.
Claims17
A method for fabricating a plurality of semiconductor packages,
- the method comprising the steps of:
- providing a wafer comprising a front side and a back side opposite the front side, the wafer including a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs), each MOSFET of the plurality of MOSFETs comprising
- a source electrode, a gate electrode, and a drain electrode positioned at the front side of the wafer;
- and
- a plurality of partial drain plugs extending a first depth from the front side into the wafer, the plurality of partial drain plugs connected to the drain electrode;
- forming a redistribution layer on the front side of the wafer;
- forming a peripheral recess on a top portion of each MOSFET;
- forming a first molding encapsulation filling the peripheral recess of each MOSFET, and enclosing sidewalls of the redistribution layer;
- grinding the back side of the wafer forming a thinned wafer;
- depositing a metal layer on a back side of the thinned wafer;
- and
- applying a singulation process so as forming the plurality of semiconductor packages;
- wherein the step of grinding the back side of the wafer forming the thinned wafer further grinds the back side of the wafer to maintain a space between a bottom of the plurality of partial drain plugs to the back side of the thinned wafer not more than 25% of a thickness of the thinned wafer.
10 more elements
A semiconductor package comprising:
- a metal-oxide-semiconductor field-effect transistor (MOSFET) comprising
- a source electrode, a gate electrode, and a drain electrode positioned at a front side of the MOSFET;
- and
- a plurality of partial drain plugs extending a first depth from the front side into the MOSFET, the plurality of partial drain plugs connected to the drain electrode;
- a redistribution layer attached to the front side of the MOSFET;
- a metal layer attached to a back side of the MOSFET;
- a conductive adhesive layer attached to a back side of the metal layer;
- and
- a metal supporting structure attached to a back side of the conductive adhesive layer,
- wherein a space between a bottom of the plurality of partial drain plugs to the metal layer is not more than 25% of a thickness of the MOSFET.
7 more elements
A semiconductor package comprising:
- a metal-oxide-semiconductor field-effect transistor (MOSFET) comprising
- a source electrode, a gate electrode, and a drain electrode positioned at a front side of the MOSFET;
- and
- a plurality of partial drain plugs extending a first depth from the front side into the MOSFET, the plurality of partial drain plugs connected to the drain electrode;
- a redistribution layer attached to the front side of the MOSFET;
- a first molding encapsulation enclosing sidewalls of the redistribution layer;
- and
- a metal layer attached to a back side of the MOSFET, wherein a space between a bottom of the plurality of partial drain plugs to the metal layer is not more than 25% of a thickness of the MOSFET.
5 more elements
A semiconductor package comprising:
- a metal-oxide-semiconductor field-effect transistor (MOSFET) comprising
- a source electrode, a gate electrode, and a drain electrode positioned at a front side of the MOSFET;
- and
- a plurality of partial drain plugs extending a first depth from the front side into the MOSFET, the plurality of partial drain plugs connected to the drain electrode;
- a redistribution layer attached to the front side of the MOSFET;
- and
- a metal layer attached to a back side of the MOSFET;
- wherein a space between a bottom of the plurality of partial drain plugs to the metal layer is not more than 25% of a thickness of the MOSFET;
- and
- wherein a depth of each of the plurality of partial drain plugs is in a range from nineteen microns to twenty-one microns;
- and wherein a thickness of the MOSFET is in a range from twenty-four microns to twenty-six microns.
8 more elements
A semiconductor package comprising:
- a metal-oxide-semiconductor field-effect transistor (MOSFET) comprising
- a source electrode, a gate electrode, and a drain electrode positioned at a front side of the MOSFET;
- and
- a plurality of partial drain plugs extending a first depth from the front side into the MOSFET, the plurality of partial drain plugs connected to the drain electrode;
- a redistribution layer attached to the front side of the MOSFET;
- and
- a metal layer attached to a back side of the MOSFET;
- wherein a space between a bottom of the plurality of partial drain plugs to the metal layer is not more than 25% of a thickness of the MOSFET;
- and
- wherein a diameter of each of the plurality of partial drain plugs is in a range from one micron to twenty microns;
- and a pitch between a selected partial drain plug of the plurality of partial drain plugs and a corresponding adjacent partial drain plug is in a range from two microns to four microns.
8 more elements
A method for fabricating a plurality of semiconductor packages, the method comprising the steps of:
- providing a wafer comprising a front side and a back side opposite the front side, the wafer including a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs), each MOSFET of the plurality of MOSFETs comprising
- a source electrode, a gate electrode, and a drain electrode positioned at the front side of the wafer;
- and
- a plurality of partial drain plugs extending a first depth from the front side into the wafer, the plurality of partial drain plugs connected to the drain electrode;
- forming a redistribution layer on the front side of the wafer;
- grinding the back side of the wafer forming a thinned wafer;
- depositing a metal layer on a back side of the thinned wafer;
- and
- applying a singulation process so as forming the plurality of semiconductor packages;
- wherein after the step of grinding the back side of the wafer, the method further comprises applying a conductive adhesive layer to a back side of the metal layer;
- and bonding a metal supporting structure to the conductive adhesive layer.
8 more elements
A method for fabricating a plurality of semiconductor packages, the method comprising the steps of:
- providing a wafer comprising a front side and a back side opposite the front side, the wafer including a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs), each MOSFET of the plurality of MOSFETs comprising
- a source electrode, a gate electrode, and a drain electrode positioned at the front side of the wafer;
- and
- a plurality of partial drain plugs extending a first depth from the front side into the wafer, the plurality of partial drain plugs connected to the drain electrode;
- forming a redistribution layer on the front side of the wafer;
- grinding the back side of the wafer forming a thinned wafer;
- depositing a metal layer on a back side of the thinned wafer;
- and
- applying a singulation process so as forming the plurality of semiconductor packages;
- wherein after the step of forming the redistribution layer, the method further comprises forming a first molding encapsulation enclosing sidewalls of the redistribution layer.
7 more elements
Dependencies are inferred from the claim text.