Semiconductor structure with test structure
AssigneeNanya Technology Corporation
InventorsTsang-Po Yang, Jui-Hsiu Jao
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Abstract
The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The plurality of unit cells are disposed in the test edge area, and the dummy area is free of the unit cells. A dimension of the test edge area in a top view is different from a dimension of the edge area in the top view.
Claims7
A semiconductor structure, comprising:
- a semiconductor substrate;
- a memory device, disposed on the semiconductor substrate and comprising:
- a device area;
- and
- an edge area, adjacent to the device area;
- and
- a test structure, disposed on the semiconductor substrate and comprising:
- a dummy area;
- a test edge area, surrounding the dummy area;
- and
- a plurality of unit cells, disposed in the test edge area, wherein the dummy area is free of the unit cells;
- wherein a dimension of the test edge area in a top view is different from a dimension of the edge area in the top view.
Dependencies are inferred from the claim text.