Vertical nanowire semiconductor device and manufacturing method therefor

A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device, the method comprising:

• forming a buffer layer on a substrate;
• forming a seed layer of catalyst material containing Ni on the buffer layer;
• forming, on the seed layer, a multilayer in which a first conductive layer, a semiconductor layer, a second conductive layer, and a metal layer are sequentially stacked;
• forming a vertical nanowire including the semiconductor layer, the second conductive layer, and the metal layer above the substrate by patterning the multilayer;
• performing metal induced crystallization (MIC) through low temperature heat treatment and producing reactant of the seed layer for crystallization, activation, and formation of a contact layer,
• wherein crystal growth started in the first conductive layer in contact with the seed layer reaches the second conductive layer in the crystallization;
• and
• the activation of the first conductive layer and the second conductive layer is induced by the crystallization;
• forming the contact layer between the second conductive layer and the metal layer while the reactant reaches the second conductive layer;
• forming an insulating layer covering the vertical nanowire;
• forming a gate surrounding a channel area by the semiconductor layer of the vertical nanowire;
• and
• forming a metal pad electrically connected to the gate, the first conductive layer, and the second conductive layer;
• the vertical nanowire semiconductor device comprising:
• the substrate;
• the buffer layer formed on the substrate;
• the first conductive layer, non-dopant implanted, in a source or drain area formed on the buffer layer, wherein a crystal structure thereof is grown in <111> orientation;
• a single crystal grain semiconductor nanowire of the channel area vertically upright with respect to the substrate on the buffer layer, wherein a crystal structure thereof is grown in <111> orientation of a single crystal grain;
• the second conductive layer of a drain or source area, non-implanted and directly formed on a top of the single crystal grain semiconductor nanowire, wherein a crystal structure thereof is grown in <111> orientation;
• a non-dopant implanted NiSi2 contact layer directly formed on a top of the second conductive layer;
• the metal layer directly formed on a top of the NiSi2 contact layer;
• the gate surrounding the channel area of the vertical nanowire and being tubular shaped;
• and
• a tubular shaped gate insulating layer located between the channel area and the tubular shaped gate.