Simulating memory cell sensing for testing sensing circuitry

A method of testing a semiconductor die, the method comprising:

• establishing voltages on sense nodes in sense amplifiers on the semiconductor die when the sense amplifiers are not connected to a memory structure having non-volatile memory cells, wherein the voltages correspond to a data pattern that is simulated as being stored in the non-volatile memory cells;
• verifying correct function of a sense operation of the semiconductor die based on the established voltages on the sense nodes;
• controlling the sense amplifiers to sense non-volatile memory cells in the memory structure when the sense amplifiers are connected to the memory structure;
• and
• providing data from sensing the non-volatile memory cells in the memory structure to a requestor external to the semiconductor die.

A control semiconductor die comprising:

• a plurality of sense amplifiers, each sense amplifier configured to be connected to a bit line in a memory structure semiconductor die having a memory structure that comprises bit lines and non-volatile memory cells, each sense amplifier having a sense node configured to sense a physical condition of a memory cell in the memory structure;
• and
• system control logic in communication with the plurality of sense amplifiers, the system control logic configured to control die level memory operations in the memory structure, the system control logic configured to:
• control a sense operation that senses a physical condition of memory cells when the sense amplifiers are connected to the bit lines of the memory structure semiconductor die;
• manipulate voltages on the sense nodes to simulate sensing a data pattern stored in memory cells of the memory structure semiconductor die when the sense amplifiers are not connected to the bit lines of the memory structure semiconductor die;
• and
• verify correct function of the sense operation performed by the system control logic based on the manipulated voltages on the sense nodes.