Memory system including parities written to dummy memory cell groups

A memory system, comprising:

• a nonvolatile memory including m planes each provided with n word lines (where n is an integer of 2 or more and m is an integer of 2 to n), n memory cell groups each including a plurality of memory cells, q dummy word lines (where q is an integer of 2 or more), and q dummy memory cell groups each including a plurality of memory cells, the nonvolatile memory being configured such that an x-th memory cell group (where x is an integer of 1 to n) that is connected to an x-th word line, a w-th dummy memory cell group (where w is an integer of 1 to q−1) that is connected to a w-th dummy word line, and in a z-th dummy memory cell group (where z is an integer of w+1 to q) that is connected to a z-th dummy word line are connected to each other in series;
• and
• a memory controller configured to generate 1-st to m-th parities using m combinations of 1-st to n-th data, respectively, wherein
• the memory controller is configured to:
• write i-th data (where i is an integer of 1 to n) to a memory cell group connected to an i-th word line of any of the m planes, such that k-th to (k+m−1)-th data (where k is an integer of 1 to n-m) are each written by a multiple bit level method to a plurality of memory cells in different planes, respectively, and
• write each of the 1-st to m-th parities by a single bit level method to any of the q dummy memory cell groups in any of the m planes,
• the nonvolatile memory further includes a (n+1)-th memory cell group that includes a plurality of memory cells, and
• the memory controller is configured to:
• store one-bit data in each of the memory cells in the (n+1)-th memory cell group to store the m pieces of 1-st to n-th data in the (n+1)-th memory cell group, and
• generate the 1-st to m-th parities by using the m pieces of 1-st to n-th data read from the (n+1)-th memory cell group,
• write a portion of the generated 1-st to m-th parities to 1-st to p-th dummy memory cell groups (where p is an integer of greater than 1 or more and less than q),
• write the m pieces of 1-st to n-th read data to the 1-st to n-th memory cell groups after writing to the 1-st to p-th dummy memory cell groups, and
• write the other parities of the 1-st to m-th generated parities to (p+1)-th to g-th dummy memory cell groups after writing to the 1-st to n-th memory cell groups,
• one memory cell in the p-th dummy memory cell group and one memory cell in the 1-st memory cell group are connected to each other in series, and
• one memory cell in the n-th memory cell group and one memory cell in the (p+1)-th dummy memory cell group are connected to each other in series.