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US 11,699,497 B2Granted
Shift register, semiconductor device, display device, and electronic device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorAtsushi Umezaki
Life of this patent
Estimating the term…
Abstract
In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.
Claims5
A semiconductor device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- and
- a fourth transistor,
- wherein one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and an output terminal are electrically connected to one another,
- wherein a gate of the first transistor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor are electrically connected to one another,
- wherein a gate of the second transistor and a gate of the third transistor are electrically connected to one another,
- wherein a gate signal line is electrically connected to the output terminal,
- wherein a power source line is electrically connected to the other of the source and the drain of the second transistor, and the other of the source and the drain of the third transistor,
- wherein a clock signal line is electrically connected to the other of the source and the drain of the first transistor, and
- wherein, in a top view, a first conductive layer, a second conductive layer, and a third conductive layer are arranged so that the first conductive layer functioning as the power source line is located between the second conductive layer functioning as the clock signal line and the third conductive layer functioning as the output terminal, and the second conductive layer functioning as the clock signal line is not located between the first conductive layer functioning as the power source line and the third conductive layer functioning as the output terminal.
9 more elements
A semiconductor device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- and
- a fourth transistor,
- wherein one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and an output terminal are electrically connected to one another,
- wherein a gate of the first transistor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor are electrically connected to one another,
- wherein a gate of the second transistor and a gate of the third transistor are electrically connected to one another,
- wherein a fourth conductive layer comprises a region serving as the gate of the second transistor and a region serving as the gate of the third transistor,
- wherein a gate signal line is electrically connected to the output terminal,
- wherein a power source line is electrically connected to the other of the source and the drain of the second transistor, and the other of the source and the drain of the third transistor,
- wherein a clock signal line is electrically connected to the other of the source and the drain of the first transistor, and
- wherein, in a top view, a first conductive layer, a second conductive layer, and a third conductive layer are arranged so that the first conductive layer functioning as the power source line is located between the second conductive layer functioning as the clock signal line and the third conductive layer functioning as the output terminal, and the second conductive layer functioning as the clock signal line is not located between the first conductive layer functioning as the power source line and the third conductive layer functioning as the output terminal.
10 more elements
A semiconductor device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- and
- a fourth transistor,
- wherein one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and an output terminal are electrically connected to one another,
- wherein a gate of the first transistor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor are electrically connected to one another,
- wherein a gate of the second transistor and a gate of the third transistor are electrically connected to one another,
- wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fourth transistor,
- wherein a first conductive layer comprises a region serving as the gate of the second transistor and a region serving as the gate of the third transistor,
- wherein a second conductive layer comprises a region serving as the other of the source and the drain of the second transistor and a region serving as the other of the source and the drain of the third transistor,
- wherein a gate signal line is electrically connected to the output terminal,
- wherein a power source line is electrically connected to the other of the source and the drain of the second transistor, and the other of the source and the drain of the third transistor,
- wherein a clock signal line is electrically connected to the other of the source and the drain of the first transistor,
- wherein, in a top view, the power source line is located between the clock signal line and the output terminal, and the clock signal line is not located between the power source line and the output terminal,
- wherein a channel width of the first transistor is larger than a channel width of the second transistor,
- wherein the channel width of the first transistor is larger than a channel width of the third transistor, and
- wherein the channel width of the first transistor is larger than a channel width of the fourth transistor.
15 more elements
Dependencies are inferred from the claim text.