Anti-fuse memory circuit

An anti-fuse memory circuit, comprising:

• a memory array, comprising a plurality of anti-fuse memory cells, the anti-fuse memory cell representing stored 1-bit data by whether a gate oxide layer is broken down;
• bit lines, each of which is connected to the anti-fuse memory cells arranged in an extension direction of the bit line, each anti-fuse memory cell being electrically connected to a respective one of the bit lines through a first switch transistor;
• word lines, each of which is connected to the first switch transistors arranged in an extension direction of the word line and configured to turn on a selected first switch transistor according to a row strobe signal, wherein the extension direction of the bit line and the extension direction of the word line are perpendicular to each other;
• a second switch transistor, configured to connect one of the bit lines to a transmission wire;
• a reading circuit, comprising a first input terminal, a second input terminal and a sampling input terminal, wherein the first input terminal is connected to the transmission wire, the second input terminal is configured to receive a reference voltage, and the sampling input terminal is configured to receive a sampling signal;
• and
• a signal generation circuit, configured to generate the sampling signal according to a precharge voltage and a precharge signal, wherein the precharge signal is used for instructing to precharge the transmission wire to the precharge voltage, and a delay duration between the sampling signal and the precharge signal is positively correlated with a voltage amplitude of the precharge voltage,
• wherein when the sampling signal is a valid pulse, the reading circuit compares an input voltage of the first input terminal with the reference voltage, to output the 1-bit data stored in the anti-fuse memory cell.