Peak and average ICC reduction by tier-based sensing during program verify operations of non-volatile memory structures

A memory controller, comprising:

• a first port configured to couple to a non-volatile memory structure, the structure comprising a memory block;
• and
• the memory controller configured to:
• during a program verify operation:
• select only a partial segment of memory cells of the memory block for bit scan mode;
• apply a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells;
• and
• initiate a bit scan mode of the selected memory cells.

A non-volatile memory system, comprising:

• a memory structure;
• a memory controller coupled to the memory structure and:
• during a program verify operation of a memory block of the memory structure:
• selecting only a partial segment of memory cells of a memory block for bit scan mode;
• applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells;
• and
• initiating a bit scan mode of the selected memory cells.