Storage system for enhancing data valid windows of signals

A storage system, comprising:

• a memory controller which provides a clock signal;
• a buffer which receives the clock signal from the memory controller and re-drives the clock signal;
• and
• a nonvolatile memory which includes a first comparator sensing a duty ratio of the clock signal, a first logic generating a first digital code regarding the duty ratio of the clock signal, a first duty cycle corrector receiving the clock signal and the first digital code and outputting a corrected clock signal by performing a first duty correction operation on the clock signal, and a data strobe signal generator generating a data strobe signal based on the corrected clock signal and providing the data strobe signal to the buffer,
• wherein the buffer includes a second comparator which senses a duty ratio of the data strobe signal received from the nonvolatile memory, a second logic which generates a second digital code regarding the duty ratio of the data strobe signal, and a second duty cycle corrector which receives the clock signal and the second digital code and performs a second duty correction operation on the clock signal.

A storage system, comprising:

• a memory controller which provides a clock signal;
• a buffer which receives the clock signal output from the memory controller and re-drives the clock signal;
• a first nonvolatile memory which includes a first duty cycle corrector receiving the clock signal from the buffer through a first channel and outputting a first corrected clock signal by performing a first duty correction operation on the clock signal, and includes a first data strobe signal generator generating a first data strobe signal based on the first corrected clock signal and providing the first data strobe signal to the buffer;
• and
• a second nonvolatile memory which includes a second duty cycle corrector receiving the clock signal from the buffer through a second channel different from the first channel and outputting a second corrected clock signal by performing a second duty correction operation on the clock signal, and includes a second data strobe signal generator generating a second data strobe signal based on the second corrected clock signal and providing the second data strobe signal to the buffer,
• wherein the buffer senses a first duty ratio of the first data strobe signal received from the first nonvolatile memory through the first channel, performs a third duty correction operation on the first duty ratio, senses a second duty ratio of the second data strobe signal received from the second nonvolatile memory through the second channel, and performs a fourth duty correction operation on the second duty ratio,
• wherein:
• the first nonvolatile memory further includes a first comparator which senses a duty ratio of the clock signal, and a first logic which generates a first digital code regarding the duty ratio of the clock signal,
• the second nonvolatile memory further includes a second comparator which senses the duty ratio of the clock signal, and a second logic which generates a second digital code regarding the duty ratio of the clock signal, and
• the buffer further includes a third comparator which senses the first duty ratio of the first data strobe signal, a third logic which generates a third digital code regarding the first duty ratio of the first data strobe signal, a fourth comparator which senses the second duty ratio of the second data strobe signal, and a fourth logic which generates a fourth digital code regarding the second duty ratio of the second data strobe signal.